07-09-2009 05:48 PM
I used to use quartus, but now an ISE guy
in quartus, there's the so-called "virtual pin",which is quite useful for IP core design, cuz we don't have to connect the pin of the core to the real pin on the board, but just treated it as a virtual one
i'm wondering whether ISE also has such a kind of thing
thx for anyone help n_n
07-09-2009 11:23 PM
07-10-2009 03:10 AM
07-13-2009 07:37 PM
not totally for timing consideration.
if there exists an IP CORE with 1000 IOs, that far more than the real PINs the FPGA device has.
so if i'd simulate this CORE, it seems i can't place all of the IOs onto the PINs, so maybe i need
the so called "virtual pin", that just treat the IOs as virtual IO, and they would just place in the DEVICE and not in the PINs