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Visitor windingyeh
Visitor
5,888 Views
Registered: ‎07-07-2009

Does ISE have a function as the "virtual pin" in QUARTUS?

I used to use quartus, but now an ISE guy

 

in quartus, there's the so-called  "virtual pin",which is quite useful for IP core design, cuz we don't have to connect the pin of the core to the real pin on the board, but just treated it as a virtual one

 

and so

i'm wondering whether ISE also has such a kind of thing

 

thx for anyone help  n_n

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Advisor evgenis1
Advisor
5,875 Views
Registered: ‎12-03-2007

Re: Does ISE have a function as the "virtual pin" in QUARTUS?

There is a Virtual IO (VIO) core that you can connect to the ICON core. Then you can access those virtual pins from the ChipScope.

 

 

 OutputLogic

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Xilinx Employee
Xilinx Employee
5,869 Views
Registered: ‎11-28-2007

Re: Does ISE have a function as the "virtual pin" in QUARTUS?

If this is for timing analysis purpose, take a look at "TPSYNC" constraint in the constraint guide (http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf).

 

Cheers,

Jim

 

Cheers,
Jim
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Visitor windingyeh
Visitor
5,824 Views
Registered: ‎07-07-2009

Re: Does ISE have a function as the "virtual pin" in QUARTUS?

not totally for timing consideration.

for example

if there exists an IP CORE with 1000 IOs, that far more than the real PINs the FPGA device has.

so if i'd simulate this CORE, it seems i can't place all of the IOs onto the PINs, so maybe i need

the so called "virtual pin", that just treat the IOs as virtual IO, and they would just place in the DEVICE and not in the PINs

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