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a4speaker
Explorer
Explorer
18,355 Views
Registered: ‎06-19-2014

[Drc 23-20] Rule violation (REQP-1712) Input clock driver

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I am using vivado 2014.2 and targetting AC701 board.

 

I have a differential clock signal at clock capable MRCC pins.

 

My clocking scheme is IBUFGDS -- > BUFG --> PLL(which drives BUFG) --> rest of design

 

At generate bit stream step I get following DRC error

 

[Drc 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal clock_gen_69/inst/clk_556_mhz on the clock_gen_69/inst/plle2_adv_inst/CLKIN1 pin of clock_gen_69/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.

 

UG472 on page 64 says that PLL/MMCM can have BUFG at input.

 

Then why is this error popping up?

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vemulad
Xilinx Employee
Xilinx Employee
29,019 Views
Registered: ‎09-20-2012

Hi,

 

Can you try running the design in latest Vivado 2014.4?

 

The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.

 

Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
29,020 Views
Registered: ‎09-20-2012

Hi,

 

Can you try running the design in latest Vivado 2014.4?

 

The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.

 

Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

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a4speaker
Explorer
Explorer
18,012 Views
Registered: ‎06-19-2014

The same problem came in vivado 2015.1. But your solution worked.

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miker
Xilinx Employee
Xilinx Employee
14,740 Views
Registered: ‎11-30-2007

I suspect that you are generating your Clocking Wizard (MMCM/PLL) Out-Of-Context which means the Clocking Wizard IP is generated/synthesized out-of-context of the higher level design.  At the time of generation for the Out-Of-Context flow, the Clocking Wizard is uninformed of where the CLKIN1 input is coming from so it defaults to the COMPENSATION=ZHOLD.  If you synthesize the Clocking Wizard with the rest of the design (i.e. “Global”) then Vivado synthesis will recognize the CLKIN1 path and correctly set the COMPENSATION of the Clocking Wizard.

 

You can accomplish this by right clicking on your XCI file in the Sources window and then select “Generate Output Products...”  Select the Synthesis Options as “Global” (versus the “Out-Of-Context Per IP”) and then select the “Generate” button.  Now, please try your implementation.

 

Thank you.

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jproch
Visitor
Visitor
11,667 Views
Registered: ‎01-29-2017

Hello all, 

I am unfortunately hitting the same error in Vivado 2016.4  :-(

zhold_err.gif

I am a newbie so I might be missing something obvious, but whatever I tried, it just ended with this error. (I did generate the "Global" Output product)

Wouldn't anybody have any idea what I am doing wrong ?

Thanks a lot!

Ian

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jproch
Visitor
Visitor
11,573 Views
Registered: ‎01-29-2017

It looks like Vivado bug, because changing Clocking Wizard primitive from PLL to MMCM "solved" the issue.
Would there be a way around it to use Clocking Wizard with the simpler PLL primitive ?

jproch
Visitor
Visitor
11,569 Views
Registered: ‎01-29-2017
I hope I found the solution. The Clocking Wizard-> Re-custom IP->PLLE2 Settings tab->"Allow Override Mode" check->Compensation set to BUF_IN.
helmutforren
Scholar
Scholar
10,796 Views
Registered: ‎06-23-2014
I just had the same problem. Regenerating and selecting "Global" fixed the problem. I wish "Global" was the default for the pop-up window!
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mkarwat
Contributor
Contributor
6,585 Views
Registered: ‎03-19-2015

2018.1 and the bug is still there. It is reasonable that with OOC the tool cannot chose the compensation method correctly as it doesn't know where the PLL will be connected, still in the documentation (7 Series FPGAs Clocking Resources User Guide page 88) we can read:

 

The COMPENSATION attribute values are documented for informational purpose only. The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at the default value.

 

And OOC is a default option...