04-06-2015 02:59 AM
I am using vivado 2014.2 and targetting AC701 board.
I have a differential clock signal at clock capable MRCC pins.
My clocking scheme is IBUFGDS -- > BUFG --> PLL(which drives BUFG) --> rest of design
At generate bit stream step I get following DRC error
[Drc 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal clock_gen_69/inst/clk_556_mhz on the clock_gen_69/inst/plle2_adv_inst/CLKIN1 pin of clock_gen_69/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
UG472 on page 64 says that PLL/MMCM can have BUFG at input.
Then why is this error popping up?
04-06-2015 03:08 AM - edited 04-06-2015 03:09 AM
Hi,
Can you try running the design in latest Vivado 2014.4?
The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.
Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
Thanks,
Deepika.
04-06-2015 03:08 AM - edited 04-06-2015 03:09 AM
Hi,
Can you try running the design in latest Vivado 2014.4?
The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.
Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
Thanks,
Deepika.
06-09-2015 10:45 PM
The same problem came in vivado 2015.1. But your solution worked.
06-21-2016 04:57 AM
I suspect that you are generating your Clocking Wizard (MMCM/PLL) Out-Of-Context which means the Clocking Wizard IP is generated/synthesized out-of-context of the higher level design. At the time of generation for the Out-Of-Context flow, the Clocking Wizard is uninformed of where the CLKIN1 input is coming from so it defaults to the COMPENSATION=ZHOLD. If you synthesize the Clocking Wizard with the rest of the design (i.e. “Global”) then Vivado synthesis will recognize the CLKIN1 path and correctly set the COMPENSATION of the Clocking Wizard.
You can accomplish this by right clicking on your XCI file in the Sources window and then select “Generate Output Products...” Select the Synthesis Options as “Global” (versus the “Out-Of-Context Per IP”) and then select the “Generate” button. Now, please try your implementation.
Thank you.
01-29-2017 10:58 PM
Hello all,
I am unfortunately hitting the same error in Vivado 2016.4 :-(
I am a newbie so I might be missing something obvious, but whatever I tried, it just ended with this error. (I did generate the "Global" Output product)
Wouldn't anybody have any idea what I am doing wrong ?
Thanks a lot!
Ian
02-02-2017 08:48 PM
It looks like Vivado bug, because changing Clocking Wizard primitive from PLL to MMCM "solved" the issue.
Would there be a way around it to use Clocking Wizard with the simpler PLL primitive ?
02-02-2017 09:01 PM
04-03-2017 09:38 AM
08-23-2018 01:40 AM - edited 08-23-2018 01:41 AM
2018.1 and the bug is still there. It is reasonable that with OOC the tool cannot chose the compensation method correctly as it doesn't know where the PLL will be connected, still in the documentation (7 Series FPGAs Clocking Resources User Guide page 88) we can read:
And OOC is a default option...