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Visitor saranb89
Visitor
11,323 Views
Registered: ‎09-12-2014

[Drc 23-20] Rule violation (RTRES-1) in bitstream generation and [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Hi,

I am trying to implement xapp524 for vc707.

I am encountering the following error in bitstream generation (vivado).

[Drc 23-20] Rule violation (RTRES-1) Backbone resources - 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are O.

 

I have the following defined in the xdc file:

 

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets Sys_Clk_p_pin];

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins {Apps_AdcToplevel_I_AppsClock/MmcmClock_I_Mmcm_Adv/CLKIN1}];

 

where, Sys_Clk_p_pin is a user sma clock.

 

 

If I don't set CLOCK_DEDICATED_ROUTE BACKBONE, then implementation fails with the following error:

 

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. 

Apps_AdcToplevel_I_Ibuf_SysClk (IBUFDS.O) is locked to IOB_X0Y74
Apps_AdcToplevel_I_AppsClock/MmcmClock_I_Mmcm_Adv (MMCME2_ADV.CLKIN1) is locked to MMCME2_ADV_X0Y6

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
Apps_AdcToplevel_I_AppsClock/MmcmClock_I_Mmcm_Adv (MMCME2_ADV.CLKOUT0) is locked to MMCME2_ADV_X0Y6
xlnx_opt_BUFG (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y18

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
Apps_AdcToplevel_I_AppsClock/MmcmClock_I_Mmcm_Adv (MMCME2_ADV.CLKOUT1) is locked to MMCME2_ADV_X0Y6
C_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y16

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
Apps_AdcToplevel_I_AppsClock/MmcmClock_I_Mmcm_Adv (MMCME2_ADV.CLKOUT3) is locked to MMCME2_ADV_X0Y6
IntMmcm_SysClk3_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y17

Clock Rule: rule_mmcm_mmcm
Status: PASS
Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
each other (vertically), if the CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set
Apps_AdcToplevel_I_AppsClock/MmcmClock_I_Mmcm_Adv (MMCME2_ADV.CLKFBOUT) is locked to MMCME2_ADV_X0Y6
and Apps_AdcToplevel_I_AppsClock/MmcmClock_I_Mmcm_Adv (MMCME2_ADV.CLKFBIN) is locked to MMCME2_ADV_X0Y6

 

How to solve these errors? 

Thanks.

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
18,681 Views
Registered: ‎07-11-2011

Re: [Drc 23-20] Rule violation (RTRES-1) in bitstream generation and [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

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HI,

 

This issue is scheduled for fix, meanwhile you can use tcl.pre to supress the bitgen warning, please refer below link

http://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-RTRES-1/m-p/488764#M9778

 

Also you can use atatched file for reference

 

Hope this helps

 

-Vanitha

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5 Replies
Xilinx Employee
Xilinx Employee
18,682 Views
Registered: ‎07-11-2011

Re: [Drc 23-20] Rule violation (RTRES-1) in bitstream generation and [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

Jump to solution

HI,

 

This issue is scheduled for fix, meanwhile you can use tcl.pre to supress the bitgen warning, please refer below link

http://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-RTRES-1/m-p/488764#M9778

 

Also you can use atatched file for reference

 

Hope this helps

 

-Vanitha

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Xilinx Employee
Xilinx Employee
11,298 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (RTRES-1) in bitstream generation and [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Hi @saranb89 

 

Which version of Vivado are you using?

 

The issue described in other thread is already fixed in latest Vivado 2014.4

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor saranb89
Visitor
11,277 Views
Registered: ‎09-12-2014

Re: [Drc 23-20] Rule violation (RTRES-1) in bitstream generation and [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Thanks. I am using vivado 2014.1. I will upgrade to 2014.4. 

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Xilinx Employee
Xilinx Employee
11,275 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (RTRES-1) in bitstream generation and [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Hi,

Ok. This issue has been fixed in Vivado 2014.3. So you can either install 2014.3 or latest 2014.4.

Thanks,
Deepika.
Thanks,
Deepika.
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Newbie pbazarnik
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Registered: ‎01-22-2018

Issue shows up in Vivado v2017.4 Re: [Drc 23-20] Rule violation (RTRES-1) in bitstream generation and [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

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I came across what seems to be the same issue as in version 2014 (see threads below)

I wonder, if this is the tool issue or the problem is on my side. (the 2014 pre.tcl fix worked, MIG seems to run fine)

 

Issue popped up in 2017:

https://forums.xilinx.com/t5/Implementation/Confused-about-clock-vs-MMCM-placement/m-p/805618/highlight/true#M19141

 

BTW I'm testing simple desgin with MIG DDR3 and TG so I can supply all design files if needed.

 

Cheers,

Przemek

 

 

Description of issue:

------------------------------------------------

 

 

Bitstream generation for Digilent Genesys 2 (see below for device info and bitstream log) fails with:

 

[DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_clk_ibuf/sys_clk_ibufg.

 

 

Earlier warning (see commened out section) was fixed by set_property:

 

 

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_clk_ibuf/sys_clk_ibufg]

# [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
#     < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_clk_ibuf/sys_clk_ibufg] >
#
#     u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y76
#      u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
#
#     The above error could possibly be related to other connected instances. Following is a list of
#     all the related clock rules and their respective instances.
#
#     Clock Rule: rule_gclkio_bufg
#     Status: PASS
#     Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip
#     as the BUFG
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y76
#      u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/clk_ref_200.u_bufg_clk_ref (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
#
#     Clock Rule: rule_gclkio_pll_1load
#     Status: PASS
#     Rule Description: An IOB driving a single PLL must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
#     is NOT set
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y76
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X1Y1
#
#     Clock Rule: rule_mmcm_bufg
#     Status: PASS
#     Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
#      u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
#      u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
#
#     Clock Rule: rule_mmcm_mmcm
#     Status: PASS
#     Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
#     each other (vertically), if the  CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set
#      u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
#      u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
#
#     Clock Rule: rule_pll_bufhce
#     Status: PASS
#     Rule Description: A PLL driving a BUFH must both be in the same horizontal row (clockregion-wise)
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKOUT3) is locked to PLLE2_ADV_X1Y1
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y19
#
#     Clock Rule: rule_bufh_bufr_ramb
#     Status: PASS
#     Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
#     than the capacity of the region
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y19
#
#     Clock Rule: rule_bufhce_mmcm
#     Status: PASS
#     Rule Description: A BUFH driving an MMCM must both be in the same clock region
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y19
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKIN1) is locked to MMCME2_ADV_X1Y1
#
#     Clock Rule: rule_mmcm_bufg
#     Status: PASS
#     Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
#      u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKFBOUT) is locked to MMCME2_ADV_X1Y1
#      and u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2
#

 

 

MIG generated constraint header:

------------------------------------------------

 

##################################################################################################
##
##  Xilinx, Inc. 2010            www.xilinx.com
##  Tue Jan 23 10:53:39 2018
##  Generated by MIG Version 4.0
##
##################################################################################################
##  File name :       example_top.xdc
##  Details :     Constraints file
##                    FPGA Family:       KINTEX7
##                    FPGA Part:         XC7K325T-FFG900
##                    Speedgrade:        -2
##                    Design Entry:      VERILOG
##                    Frequency:         0 MHz
##                    Time Period:       1250 ps
##################################################################################################

##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-107
## Data Width: 32
## Time Period: 1250
## Data Mask: 1
##################################################################################################
############## NET - IOSTANDARD ##################

 

 

Run log:

------------------


*** Running vivado
    with args -log example_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_top.tcl -notrace


****** Vivado v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
  **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source example_top.tcl -notrace
Command: link_design -top example_top -part xc7k325tffg900-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint '/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.srcs/sources_1/ip/mig_7series_0/mig_7series_0.dcp' for cell 'u_mig_7series_0'
INFO: [Netlist 29-17] Analyzing 853 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/imports/example_top.xdc]
Finished Parsing XDC File [/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/imports/example_top.xdc]
Parsing XDC File [/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc] for cell 'u_mig_7series_0'
Finished Parsing XDC File [/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc] for cell 'u_mig_7series_0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 292 instances were transformed.
  IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT, IBUFDS_IBUFDISABLE_INT, INV, OBUFTDS_DCIEN, OBUFTDS_DCIEN): 4 instances
  IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 229 instances

8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.645 ; gain = 470.234 ; free physical = 2902 ; free virtual = 121690
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1745.680 ; gain = 64.031 ; free physical = 2895 ; free virtual = 121684
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 2 inverter(s) to 2 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 152b8fa90

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.97 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2473 ; free virtual = 121262
INFO: [Opt 31-389] Phase Retarget created 51 cells and removed 112 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 7 inverter(s) to 21 load pin(s).
Phase 2 Constant propagation | Checksum: 143d04acd

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2469 ; free virtual = 121262
INFO: [Opt 31-389] Phase Constant propagation created 215 cells and removed 399 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: d8823ea9

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2466 ; free virtual = 121260
INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 1133 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: d8823ea9

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2466 ; free virtual = 121260
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: d8823ea9

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2472 ; free virtual = 121261
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2472 ; free virtual = 121260
Ending Logic Optimization Task | Checksum: 10cefbc18

Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2467 ; free virtual = 121261

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1025785c6

Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2242.320 ; gain = 0.000 ; free physical = 2467 ; free virtual = 121260
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2242.320 ; gain = 568.676 ; free physical = 2467 ; free virtual = 121260
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2266.332 ; gain = 0.000 ; free physical = 2460 ; free virtual = 121256
INFO: [Common 17-1381] The checkpoint '/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.runs/impl_1/example_top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file example_top_drc_opted.rpt -pb example_top_drc_opted.pb -rpx example_top_drc_opted.rpx
Command: report_drc -file example_top_drc_opted.rpt -pb example_top_drc_opted.pb -rpx example_top_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.runs/impl_1/example_top_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2306.352 ; gain = 0.000 ; free physical = 2439 ; free virtual = 121237
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1c2240b

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2306.352 ; gain = 0.000 ; free physical = 2438 ; free virtual = 121236
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2306.352 ; gain = 0.000 ; free physical = 2441 ; free virtual = 121240

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17e692d37

Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2306.352 ; gain = 0.000 ; free physical = 2410 ; free virtual = 121208

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1b9f661b4

Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2348.004 ; gain = 41.652 ; free physical = 2359 ; free virtual = 121157

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b9f661b4

Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2348.004 ; gain = 41.652 ; free physical = 2359 ; free virtual = 121157
Phase 1 Placer Initialization | Checksum: 1b9f661b4

Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2348.004 ; gain = 41.652 ; free physical = 2359 ; free virtual = 121157

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 19bdb05c1

Time (s): cpu = 00:00:38 ; elapsed = 00:00:15 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2305 ; free virtual = 121103

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 19bdb05c1

Time (s): cpu = 00:00:38 ; elapsed = 00:00:15 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2305 ; free virtual = 121103

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1934aa620

Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2297 ; free virtual = 121095

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1e16e1dde

Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2297 ; free virtual = 121095

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1eb4b3317

Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2297 ; free virtual = 121095

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1eb4b3317

Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2297 ; free virtual = 121095

Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 1eb4b3317

Time (s): cpu = 00:00:44 ; elapsed = 00:00:17 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2297 ; free virtual = 121095

Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 13f3fe699

Time (s): cpu = 00:00:48 ; elapsed = 00:00:22 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2280 ; free virtual = 121078

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 2022fbea6

Time (s): cpu = 00:00:49 ; elapsed = 00:00:22 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2280 ; free virtual = 121078

Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 156c5cb46

Time (s): cpu = 00:00:49 ; elapsed = 00:00:22 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2280 ; free virtual = 121078

Phase 3.10 Fast Optimization
Phase 3.10 Fast Optimization | Checksum: 156c5cb46

Time (s): cpu = 00:00:51 ; elapsed = 00:00:23 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2283 ; free virtual = 121081
Phase 3 Detail Placement | Checksum: 156c5cb46

Time (s): cpu = 00:00:51 ; elapsed = 00:00:23 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2283 ; free virtual = 121081

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 180da24e2

Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 180da24e2

Time (s): cpu = 00:00:58 ; elapsed = 00:00:25 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2290 ; free virtual = 121088
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.201. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 107b6bec2

Time (s): cpu = 00:00:58 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2288 ; free virtual = 121087
Phase 4.1 Post Commit Optimization | Checksum: 107b6bec2

Time (s): cpu = 00:00:58 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2288 ; free virtual = 121086

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 107b6bec2

Time (s): cpu = 00:00:59 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2295 ; free virtual = 121093

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 107b6bec2

Time (s): cpu = 00:00:59 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2295 ; free virtual = 121093

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 17f529705

Time (s): cpu = 00:00:59 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2295 ; free virtual = 121093
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17f529705

Time (s): cpu = 00:00:59 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2295 ; free virtual = 121093
Ending Placer Task | Checksum: 153dace14

Time (s): cpu = 00:00:59 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2358 ; free virtual = 121157
INFO: [Common 17-83] Releasing license: Implementation
46 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:02 ; elapsed = 00:00:28 . Memory (MB): peak = 2449.695 ; gain = 143.344 ; free physical = 2358 ; free virtual = 121157
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2449.695 ; gain = 0.000 ; free physical = 2324 ; free virtual = 121151
INFO: [Common 17-1381] The checkpoint '/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.runs/impl_1/example_top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file example_top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2449.695 ; gain = 0.000 ; free physical = 2330 ; free virtual = 121134
INFO: [runtcl-4] Executing : report_utilization -file example_top_utilization_placed.rpt -pb example_top_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2449.695 ; gain = 0.000 ; free physical = 2350 ; free virtual = 121154
INFO: [runtcl-4] Executing : report_control_sets -verbose -file example_top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2449.695 ; gain = 0.000 ; free physical = 2348 ; free virtual = 121153
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Checksum: PlaceDB: 9ab39ccc ConstDB: 0 ShapeSum: b9273148 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 102433972

Time (s): cpu = 00:00:32 ; elapsed = 00:00:20 . Memory (MB): peak = 2675.910 ; gain = 211.066 ; free physical = 2082 ; free virtual = 120887
Post Restoration Checksum: NetGraph: 51cdaaf5 NumContArr: b0758e7d Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 102433972

Time (s): cpu = 00:00:32 ; elapsed = 00:00:21 . Memory (MB): peak = 2675.910 ; gain = 211.066 ; free physical = 2076 ; free virtual = 120886

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 102433972

Time (s): cpu = 00:00:33 ; elapsed = 00:00:21 . Memory (MB): peak = 2675.910 ; gain = 211.066 ; free physical = 2033 ; free virtual = 120843

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 102433972

Time (s): cpu = 00:00:33 ; elapsed = 00:00:21 . Memory (MB): peak = 2675.910 ; gain = 211.066 ; free physical = 2033 ; free virtual = 120843
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 11171f15b

Time (s): cpu = 00:00:42 ; elapsed = 00:00:24 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 2022 ; free virtual = 120827
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.116  | TNS=0.000  | WHS=-0.474 | THS=-1419.966|

Phase 2 Router Initialization | Checksum: 92dc2739

Time (s): cpu = 00:00:46 ; elapsed = 00:00:25 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 2011 ; free virtual = 120821

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1656ddda3

Time (s): cpu = 00:00:53 ; elapsed = 00:00:26 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 2004 ; free virtual = 120815

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1803
 Number of Nodes with overlaps = 79
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.116  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: de231d4a

Time (s): cpu = 00:01:16 ; elapsed = 00:00:30 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1999 ; free virtual = 120810
Phase 4 Rip-up And Reroute | Checksum: de231d4a

Time (s): cpu = 00:01:16 ; elapsed = 00:00:30 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1999 ; free virtual = 120810

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: de231d4a

Time (s): cpu = 00:01:16 ; elapsed = 00:00:30 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1999 ; free virtual = 120810

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: de231d4a

Time (s): cpu = 00:01:17 ; elapsed = 00:00:30 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1999 ; free virtual = 120810
Phase 5 Delay and Skew Optimization | Checksum: de231d4a

Time (s): cpu = 00:01:17 ; elapsed = 00:00:30 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1999 ; free virtual = 120810

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 8ca8c5a1

Time (s): cpu = 00:01:18 ; elapsed = 00:00:31 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 2000 ; free virtual = 120810
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.116  | TNS=0.000  | WHS=0.057  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 8ca8c5a1

Time (s): cpu = 00:01:18 ; elapsed = 00:00:31 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 2000 ; free virtual = 120810
Phase 6 Post Hold Fix | Checksum: 8ca8c5a1

Time (s): cpu = 00:01:18 ; elapsed = 00:00:31 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 2000 ; free virtual = 120810

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.04678 %
  Global Horizontal Routing Utilization  = 1.2729 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: a0bf4308

Time (s): cpu = 00:01:20 ; elapsed = 00:00:31 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1999 ; free virtual = 120809

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: a0bf4308

Time (s): cpu = 00:01:20 ; elapsed = 00:00:31 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1998 ; free virtual = 120808

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 137e62534

Time (s): cpu = 00:01:21 ; elapsed = 00:00:32 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1997 ; free virtual = 120808

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.116  | TNS=0.000  | WHS=0.057  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 137e62534

Time (s): cpu = 00:01:21 ; elapsed = 00:00:32 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 1999 ; free virtual = 120809
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:01:21 ; elapsed = 00:00:32 . Memory (MB): peak = 2693.781 ; gain = 228.938 ; free physical = 2059 ; free virtual = 120869

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:26 ; elapsed = 00:00:34 . Memory (MB): peak = 2693.781 ; gain = 244.086 ; free physical = 2059 ; free virtual = 120869
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2693.781 ; gain = 0.000 ; free physical = 2014 ; free virtual = 120861
INFO: [Common 17-1381] The checkpoint '/mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.runs/impl_1/example_top_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2693.781 ; gain = 0.000 ; free physical = 2044 ; free virtual = 120863
INFO: [runtcl-4] Executing : report_drc -file example_top_drc_routed.rpt -pb example_top_drc_routed.pb -rpx example_top_drc_routed.rpx
Command: report_drc -file example_top_drc_routed.rpt -pb example_top_drc_routed.pb -rpx example_top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.runs/impl_1/example_top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file example_top_methodology_drc_routed.rpt -pb example_top_methodology_drc_routed.pb -rpx example_top_methodology_drc_routed.rpx
Command: report_methodology -file example_top_methodology_drc_routed.rpt -pb example_top_methodology_drc_routed.pb -rpx example_top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 8 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /mnt/CAD_Space/home2/r1100/SVN2/QR/hardware/dev1/fpga/genesys2/mig_7series_0_ex/mig_7series_0_ex.runs/impl_1/example_top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file example_top_power_routed.rpt -pb example_top_power_summary_routed.pb -rpx example_top_power_routed.rpx
Command: report_power -file example_top_power_routed.rpt -pb example_top_power_summary_routed.pb -rpx example_top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:15 ; elapsed = 00:00:07 . Memory (MB): peak = 2867.934 ; gain = 86.109 ; free physical = 1915 ; free virtual = 120740
INFO: [runtcl-4] Executing : report_route_status -file example_top_route_status.rpt -pb example_top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file example_top_timing_summary_routed.rpt -rpx example_top_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file example_top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file example_top_clock_utilization_routed.rpt
report_clock_utilization: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2867.934 ; gain = 0.000 ; free physical = 1890 ; free virtual = 120730
Command: write_bitstream -force example_top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_clk_ibuf/sys_clk_ibufg.
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/pll_clk3_out on the u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
WARNING: [DRC RTSTAT-10] No routable loads: 1890 net(s) have no routable loads. The problem bus(es) and/or net(s) are cal2_state_r[4:0], dbg_axi_cmp_data[31:0], dbg_axi_rdata_cmp[31:0], dbg_bit[8:0], dbg_cal1_cnt_cpt_r[3:0], dbg_cal1_state_r[5:0], dbg_clear_error, dbg_cmd_wdt_err_w, dbg_cmp_addr_i[31:0], dbg_cmp_bl_i[5:0], dbg_cmp_data_r[63:0], dbg_cmp_data_valid, dbg_cmp_error, dbg_cpt_first_edge_cnt[107:0], dbg_cpt_first_edge_cnt_by_dqs[5:0]... and (the first 15 of 198 listed).
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 3 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
87 Infos, 3 Warnings, 0 Critical Warnings and 2 Errors encountered.
write_bitstream failed
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2867.934 ; gain = 0.000 ; free physical = 1881 ; free virtual = 120721
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Tue Jan 23 13:45:02 2018...

 

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