02-24-2014 03:48 AM
I am a beginner on synthesis and implementation and i am developing a university project using a Virtex 7 board.
I have got this error during the implementation phase with Vivado 2013.3:
[Vivado_Tcl 4-131] Power Optimization encountered an exception: ERROR: [Common 17-70] Application Exception: i_gnet->isConstant()
As the message says, there is an error during the Power Optimization. Actually the Log file does not even say where it encounterd the error exactly, and i have no idea what is 'i_gnet'.
The implementation works as long as i remove all the optimization settings, but doing in this way i get a very bad timing result, especially due to a clock of 500Mhz received as input on the top module and spreaded all around my logic without using any MMCM.
Does anybody know how can i correct this error or at least other ways to recover the bad timing analysis?
02-24-2014 03:54 AM - edited 02-24-2014 04:00 AM
Can you check this in vivado 2013.4?
Did you disable opt_design phase too? Rather than disabling the complete opt_design phase, you can just disable BRAM power optimization phase of opt_design. Write the below switches in more options field of opt_design.
-retarget -propconst -sweep
02-24-2014 03:58 AM
There was a known CR for this power_opt. The number is
This is fixed in 2013.4. Please try in 2013.4 and update us.
02-24-2014 04:58 AM
Thanks for your reply.
Tomorrow, once back in my office, i will upgrade vivado and try again.
However, i disabled opt_design to avoid optimizations. I will also try yout trick
02-24-2014 04:59 AM
Sure Please keep me posted. If it doesnt work in 2013.4, we have to investigate and file a CR if applicable.
02-24-2014 05:00 AM
02-24-2014 05:02 AM
02-24-2014 11:51 PM
The trick proposed by vemulad worked.
Actually i still have to upgrade Vivado to the 2013.4 version. In the next few days, i will let you know when i will have done.
In the meanwhile thanks to everyone.