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Visitor athira
Visitor
6,894 Views
Registered: ‎02-22-2009

ERROR:ConstraintSystem:59: INST "add3bit1" not found

I have a problem with my UCF file. I am using Xilinx 10.1 SP3 and working with Virtex-5. I have some modules called add3bit1, doublebit1, pass1, add2bit1 in my top-level HDL file. In my UCF file, I have the following line:

    INST "doublebit1" AREA_GROUP = AG_doublebit1 ;
    AREA_GROUP "AG_doublebit1" RANGE = SLICE_X20Y86:SLICE_X23Y89;
    AREA_GROUP "AG_doublebit1" GROUP = CLOSED;

    INST "pass1" AREA_GROUP = "AG_pass1" ;
    AREA_GROUP "AG_pass1" RANGE = SLICE_X20Y82:SLICE_X23Y85;
    AREA_GROUP "AG_pass1" GROUP = CLOSED;

    INST "add2bit1" AREA_GROUP = "AG_add2bit1" ;
    AREA_GROUP "AG_add2bit1" RANGE = SLICE_X20Y78:SLICE_X23Y81;
    AREA_GROUP "AG_add2bit1" GROUP = CLOSED;

    INST "add3bit1" AREA_GROUP = "static" ;

But when I do Translate, it fails, giving me the error message:

######################################

ERROR:ConstraintSystem:59 - Constraint <INST "doublebit1" AREA_GROUP =
   AG_doublebit1 ;> [topmod.ucf(12)]: INST "doublebit1" not found.  Please
   verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "AG_doublebit1" RANGE =
   SLICE_X20Y86:SLICE_X23Y89;> [topmod.ucf(13)]: Unable to find an active
   'Area_Group' constraint named 'AG_doublebit1'.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "AG_doublebit1" GROUP =
   CLOSED;> [topmod.ucf(14)]: Unable to find an active 'Area_Group' constraint
   named 'AG_doublebit1'.

ERROR:ConstraintSystem:59 - Constraint <INST "pass1" AREA_GROUP = "AG_pass1" ;>
   [topmod.ucf(16)]: INST "pass1" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "AG_pass1" RANGE =
   SLICE_X20Y82:SLICE_X23Y85;> [topmod.ucf(17)]: Unable to find an active
   'Area_Group' constraint named 'AG_pass1'.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "AG_pass1" GROUP = CLOSED;>
   [topmod.ucf(18)]: Unable to find an active 'Area_Group' constraint named
   'AG_pass1'.

ERROR:ConstraintSystem:59 - Constraint <INST "add2bit1" AREA_GROUP =
   "AG_add2bit1" ;> [topmod.ucf(20)]: INST "add2bit1" not found.  Please verify
   that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "AG_add2bit1" RANGE =
   SLICE_X20Y78:SLICE_X23Y81;> [topmod.ucf(21)]: Unable to find an active
   'Area_Group' constraint named 'AG_add2bit1'.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "AG_add2bit1" GROUP =
   CLOSED;> [topmod.ucf(22)]: Unable to find an active 'Area_Group' constraint
   named 'AG_add2bit1'.

ERROR:ConstraintSystem:59 - Constraint <INST "add3bit1" AREA_GROUP = "static" ;>
   [topmod.ucf(24)]: INST "add3bit1" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

######################################

I checked and double-checked. The module names are all correct. In addition to the above modules, I have even instantiated a couple of bus macros. But they do not turn in any errors. Does anyone know what could be the problem?

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Xilinx Employee
Xilinx Employee
6,881 Views
Registered: ‎08-02-2007

Re: ERROR:ConstraintSystem:59: INST "add3bit1" not found

please verify these modules are really in the design after Synthesis

synthesiser may rename them.

 

 

or you can command out these constraints first

use floorplaner to reloace them

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