UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
952 Views
Registered: ‎04-30-2019

ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

Hi,

I have an IP block for a GTY transceiver that, since moving to the Linux tools, is bombing out with the following error:

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 16 out of 39 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: ch0_gtyrxn_in, ch0_gtyrxp_in, ch0_gtytxn_out, ch0_gtytxp_out, ch1_gtyrxn_in, ch1_gtyrxp_in, ch1_gtytxn_out, ch1_gtytxp_out, ch2_gtyrxn_in, ch2_gtyrxp_in, ch2_gtytxn_out, ch2_gtytxp_out, ch3_gtyrxn_in, ch3_gtyrxp_in, ch3_gtytxn_out... and (the first 15 of 16 listed).

I upgraded to 2019.1 at the same time but have since tried to roll back to 2018.3 to see if that was the issue with no success.  The project was working on Windows and although I've made some changes to the Tcl, the IP blocks haven't changed.

In my non-project flow I generate DCP's for all IP and then read those in during synthesis and implementation.  The XDC files seem to correctly constrain the I/O.

Just to check I've also copied the package_pin constraints from the IP up to my top level XDC which had no effect.  So why are these constraints being ignored?  I've attached the XCI and XDC files from my IP as well as the logs from synth/impll/bit.

Shareef.

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
677 Views
Registered: ‎07-16-2008

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

No, I don't think the property propagates to impl. In the initial phase of implementation, a in-memory project will be created to import the synthesized sources and the operations in previous in-memory design were deprecated.

Note GUI generated Tcl scripts are executed in IDE framework and not necessarily identical to pure non-project flow.

Simply speaking, just read the IP .xci files prior to implementation. See if that allows the constraints to be obeyed. If yes, modify your Tcl script to get expected result. If not, we can continue investigation.

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

0 Kudos
17 Replies
Teacher drjohnsmith
Teacher
942 Views
Registered: ‎07-09-2009

Re: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution
It means the logic has pins that the placer does not know where to put them.

You say you have gone to to linux, I guess from windows,

I can't open the tgz file on my phone,
look in the log files for the first warning / error

Has it simulated under Linux ?

An off the shelf comment, Linux and windows have different path names, and more importantly the "/" and the "\"


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Teacher drjohnsmith
Teacher
939 Views
Registered: ‎07-09-2009

Re: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution
thinking some more about the error
it can also mean you have pins in the xdc that are not in your top
possibly due to code problems, causing logic to be un used and removed.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Xilinx Employee
Xilinx Employee
895 Views
Registered: ‎05-22-2018

Re: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

Hi shareef@phoelex.com ,

The error message is to notify that user need to set IOSTANDARD and PACKAGE_PIN, in order to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.

Please check the below AR# on detailed information on how to overcome that:

https://www.xilinx.com/support/answers/56354.html 

Thanks,

Raj

Xilinx Employee
Xilinx Employee
822 Views
Registered: ‎07-16-2008

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

If you open the implemented design, do you see the associated GTY channel locked? In addition, if you select these input ports in question, do you see PACKAGE_PIN property assigned in their properties?

In the IP XDC file, the channel primitive should be locked down, which is sufficient for GT serial data input pin constraints. If the IP XDC file is successfully read in, the constraints are expected to be applied.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
803 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

@rshekhaw , yes, thanks, I know.  Perhaps you missed the fact that this either a) works on Windows and b) is an IP block so the constraints are Xilinx generate, not my own.

@graces , thanks.  Yes, I was looking at the XDC file just now and the comments are the same regarding the IO constraints.  I'll see if I can launch the GUI and check.

@drjohnsmith , it was working before so I'm not sure what could have gone wrong.  I can't simulate it as it doesn't get through PnR.

0 Kudos
796 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

@graces , so it looks like the constraints are being ignored.  The IP XDC file locks the GTY but the location after implementation is different.

# Channel primitive location constraint
set_property LOC GTYE3_CHANNEL_X0Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[2].*gen_gtye3_channel_inst[0].GTYE3_CHANNEL_PRIM_INST}]

# Channel primitive serial data pin location constraints
# (Provided as comments for your reference. The channel primitive location constraint is sufficient.)
#set_property package_pin AR46 [get_ports gtyrxn_in[0]]
#set_property package_pin AR45 [get_ports gtyrxp_in[0]]
#set_property package_pin AT43 [get_ports gtytxn_out[0]]
#set_property package_pin AT42 [get_ports gtytxp_out[0]]

But launching the GUI I can see that Ch0 is using X0Y4.

0 Kudos
Teacher drjohnsmith
Teacher
782 Views
Registered: ‎07-09-2009

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

you simulate before sysnthesis and P&R

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
760 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

@drjohnsmith , not if you're using IP blocks that you need to generate and then use the export_simulation flow.

@graces , I've done some more debug and found one issue with my input clock assigments.  I'm using the Bullseye connector and missed that the SI570 refclk comes in on the second mgtrefclk.  However, the main issue of the tools not obeying the constraints must have hidden this issue as I've had this board up and running in the lab.  I'm guessing it randomly assigned the correct port or something.

I've also taken a step back wards and re-generated the GTY IP and a new example design.  If I include the IP in my own top level, the constraints are ignored.  I place the mgtrefclk in bank 126 but the GTY diff pairs are placed on bank 125.  However, generating the example design for the GTY seems to obey the constraints.

So what could cause the constraints to be ignored?  I'm loading in a Microblaze MCS IP as well so could that be clashing and the tools not outputting any warnings?

I'll try and remove the IP blocks one by one to get as close as I can to the GTY reference design in the meantime.

0 Kudos
747 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

I've now debugged this as far as I can and it just seems that Vivado is ignoring the GTY location constraints from the IP's XDC.  I have to copy out the individual I/O pin assignments and put them in my top level XDC for them to be obeyed.

I can tar up my project and send it to someone as a testcase for bug hunting.  Please email me @graces .

0 Kudos
Xilinx Employee
Xilinx Employee
714 Views
Registered: ‎07-16-2008

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

So does it work or not by copying IP level IO constraint to top level? From your latest reply, I understand it works. However from your initial post it does not.

"Just to check I've also copied the package_pin constraints from the IP up to my top level XDC which had no effect."

Anyway, I had a look at your log files and got to know your Tcl commands.  Proc 'read_all_ip' is called in implementation initial stage. However inside the proc, all IP XDCs are disabled to be used in implementation. I think that's why the constraints are ignored.

If you compare with example design Tcl script under the hood, you should be able to see that before link_design, you just need to run 'read_ip' commands to read individual IPs. No need to set used_in_implementation property for the associated XDC files.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
698 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

The constraints should be stored in the DCP should they not?  Your own scripts set used_in_implementation to false.

These are the commands in the example design:

read_ip -quiet /home/shareef/git/xilinx_ip_gen/gty_caui4_bullseye_25_78125_ex/gty_caui4_bullseye_25_78125_ex.srcs/sources_1/ip/gty_caui4_bullseye_25_78125/gty_caui4_bullseye_25_78125.xci
set_property used_in_implementation false [get_files -all /home/shareef/git/xilinx_ip_gen/gty_caui4_bullseye_25_78125_ex/gty_caui4_bullseye_25_78125_ex.srcs/sources_1/ip/gty_caui4_bullseye_25_78125/synth/gty_caui4_bullseye_25_78125_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/shareef/git/xilinx_ip_gen/gty_caui4_bullseye_25_78125_ex/gty_caui4_bullseye_25_78125_ex.srcs/sources_1/ip/gty_caui4_bullseye_25_78125/synth/gty_caui4_bullseye_25_78125.xdc]

read_ip -quiet /home/shareef/git/xilinx_ip_gen/gty_caui4_bullseye_25_78125_ex/gty_caui4_bullseye_25_78125_ex.srcs/sources_1/ip/gty_caui4_bullseye_25_78125_vio_0/gty_caui4_bullseye_25_78125_vio_0.xci
set_property used_in_implementation false [get_files -all /home/shareef/git/xilinx_ip_gen/gty_caui4_bullseye_25_78125_ex/gty_caui4_bullseye_25_78125_ex.srcs/sources_1/ip/gty_caui4_bullseye_25_78125_vio_0/gty_caui4_bullseye_25_78125_vio_0.xdc]
set_property used_in_implementation false [get_files -all /home/shareef/git/xilinx_ip_gen/gty_caui4_bullseye_25_78125_ex/gty_caui4_bullseye_25_78125_ex.srcs/sources_1/ip/gty_caui4_bullseye_25_78125_vio_0/gty_caui4_bullseye_25_78125_vio_0_ooc.xdc]
0 Kudos
Xilinx Employee
Xilinx Employee
692 Views
Registered: ‎07-16-2008

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

These commands are run in synthesis stage.

Compare the ones in impl_1/<top>.tcl. Reading the .xci will allow the tool to automatically manage the constraints. You do not explicitly disabling used_in_implementation property for the IP XDC files right before implementation.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
690 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

But according to your documentation the USED_IN property has both synthesis and implementation options.  So setting use_in_implementation to false in the synthesis stage should propagate to the implementation stage should it not?  If they don't then having them in the synthesis script is pointless and confusing.

0 Kudos
Xilinx Employee
Xilinx Employee
678 Views
Registered: ‎07-16-2008

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

No, I don't think the property propagates to impl. In the initial phase of implementation, a in-memory project will be created to import the synthesized sources and the operations in previous in-memory design were deprecated.

Note GUI generated Tcl scripts are executed in IDE framework and not necessarily identical to pure non-project flow.

Simply speaking, just read the IP .xci files prior to implementation. See if that allows the constraints to be obeyed. If yes, modify your Tcl script to get expected result. If not, we can continue investigation.

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

0 Kudos
675 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

OK, thanks a lot.  So from the synthesis stage viewpoint, what does a use_in_implementation property apply to?

0 Kudos
Xilinx Employee
Xilinx Employee
669 Views
Registered: ‎07-16-2008

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

My understanding is that it is by design in GUI mode. I see top level XDC files are also applied this property in synthesis.

Actually in non-project mode, you can read_xdc manually in any point of the flow. So I think the used_in property doesn't matter that much in non-project mode.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
649 Views
Registered: ‎04-30-2019

回复: ERROR: [DRC UCIO-1] Unconstrained Logical Port during bitstream generation

Jump to solution

OK, this now seems to be repeatable.  Thanks for the help.

0 Kudos