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spera
Visitor
Visitor
17,163 Views
Registered: ‎02-23-2009

ERROR:NgdBuild:604 - logical block

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Hi everybody,

I created an embedded system in EDK with a chipscope peripheral and a uBlaze.

I generated the Netlist then I back in XST and tried to generate program file

but I've got this error:

 

ERROR:NgdBuild:604 - logical block
   'chipscope_plbv46_iba_0/chipscope_plbv46_iba_0/i_chipscope_plbv46_iba_0' with
   type 'chipscope_plbv46_iba_0' could not be resolved. A pin name misspelling
   can cause this, a missing edif or ngc file, or the misspelling of a type
   name. Symbol 'chipscope_plbv46_iba_0' is not supported in target 'virtex5'.

 

Could anybody explain what this error means and how to avoid this error!

Message Edited by spera on 02-23-2009 01:30 PM
Message Edited by spera on 02-23-2009 01:31 PM
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graces
Moderator
Moderator
19,623 Views
Registered: ‎07-16-2008

Please verify that the called out netlist file is located in the macro search path or project directory.

To set the macro search path, following these steps in ISE:
1. Select the top-level source in the Source window.
2. Right-click "Implementation Process" in the Process window and select "Properties."
3. Select the "Translate Properties tab." The Macro Search Path option is available.

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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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4 Replies
graces
Moderator
Moderator
19,624 Views
Registered: ‎07-16-2008

Please verify that the called out netlist file is located in the macro search path or project directory.

To set the macro search path, following these steps in ISE:
1. Select the top-level source in the Source window.
2. Right-click "Implementation Process" in the Process window and select "Properties."
3. Select the "Translate Properties tab." The Macro Search Path option is available.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

jmpg
Contributor
Contributor
15,750 Views
Registered: ‎03-26-2009

Hello,

I have the same error than spera. Have you solved it?

 

graces, I'm using a EDK project (without ISE integration), so how can I edit the Translate Properties?

 

Thanks in advance,

 

Best Regards,

José María

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raulhuertas
Observer
Observer
13,628 Views
Registered: ‎09-12-2010

Hello y friend, did you solve his issue? I've used the macro method and i have the same error. I'm using 13.1 tools.

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santukms
Adventurer
Adventurer
13,561 Views
Registered: ‎09-15-2010

Hi ,

 

 

I did the step told by you,,,,,,

in my design the above error is removed thank you so much :):):)

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