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Visitor
Visitor
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Registered: ‎07-07-2009

ERROR:Place:1158 + ERROR:Place:1160 - Unroutable Placement!

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Hello, I have faced with some troubles during implementation process, so please help!

I use Spartan-6 (xc6slx9-2-tqg144) part and ISE 14.4 WebPack, and need to use all 4 DCMs in my project to shift clock phase by 90 degrees to recieve data from 4 independent channels, and also need 1 PLL_BASE to multiply system clock from 40 Mhz input to 160 MHz, which is my SYS_CLK inside FPGA.

During Map process I recieve following messages (where "SHIFT_90_2" is my 2nd clock phase shifter, and I have 4 of them in my project):


ERROR:Place:1158 - Unroutable Placement! A BUFIO / DCM clock component pair have
been found that are not placed at a routable BUFIO / DCM site pair. The BUFIO
component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X3Y10>.
The corresponding DCM component <SHIFT_90_2/dcm_sp_inst> is placed at site
<DCM_X0Y2>. The BUFIO can use the fast path between the BUFIO and the DCM if
the BUFIO is in TOPor BOTTOM edge and both the BUFIO & DCM are placed in the
same half of the device (TOP or BOTTOM). This placement is UNROUTABLE in PAR
and therefore, this error condition should be fixed in your design. You may
use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this
message to a WARNING in order to generate an NCD file. This NCD file can then
be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used
in this clock placement rule is listed below. These examples can be used
directly in the .ucf file to demote this ERROR to a WARNING.
< PIN "SHIFT_90_2/dcm_sp_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1160 - Unroutable Placement! A BUFIOFB / DCM clock component pair
have been found that are not placed at a routable BUFIOFB / DCM site pair.
The BUFIOFB component <SP6_INS_BUFIO2FB_DCM_ML_BUFIO2FB_6> is placed at site
<BUFIO2FB_X3Y10>. The corresponding DCM component <SHIFT_90_2/dcm_sp_inst> is
placed at site <DCM_X0Y2>. The BUFIOFB can use the fast path between the
BUFIOFB and the DCM if the BUFIOFB is in TOPor BOTTOM edge and both the
BUFIOFB & DCM are placed in the same half of the device (TOP or BOTTOM). This
placement is UNROUTABLE in PAR and therefore, this error condition should be
fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the
.ucf file to demote this message to a WARNING in order to generate an NCD
file. This NCD file can then be used in FPGA Editor to debug the problem. A
list of all the COMP.PINS used in this clock placement rule is listed below.
These examples can be used directly in the .ucf file to demote this ERROR to
a WARNING.
< PIN "SHIFT_90_2/dcm_sp_inst.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; >

 

Seems I have to force mapping by applying some ucf constraints to DCM location, or the problem is somewhere else?

Can anybody give an advice?

 

In advance thanks,

Evgenyy.

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Xilinx Employee
Xilinx Employee
6,910 Views
Registered: ‎06-20-2008
I have attached a picture that I have draw for reference. In the LX9 you have 4 DCMs so you must make sure each of the IOs driving the DCM are placed in the correct half of the device. Since the there are 4 DCMs there will be 2 in the top half of the device and 2 in the bottom half. You now must have 2 of the the clocks driving these DCMs in the top half and 2 of the clocks in the bottom half. Using the picture I attached you should be able to see which have of the device the GCLKs are in. Assign your clocks so that there are only 2 per half of the device and then the tools will be able to place the rest, as long as you have not over used any of the components.

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DCM.jpg
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Xilinx Employee
Xilinx Employee
6,911 Views
Registered: ‎06-20-2008
I have attached a picture that I have draw for reference. In the LX9 you have 4 DCMs so you must make sure each of the IOs driving the DCM are placed in the correct half of the device. Since the there are 4 DCMs there will be 2 in the top half of the device and 2 in the bottom half. You now must have 2 of the the clocks driving these DCMs in the top half and 2 of the clocks in the bottom half. Using the picture I attached you should be able to see which have of the device the GCLKs are in. Assign your clocks so that there are only 2 per half of the device and then the tools will be able to place the rest, as long as you have not over used any of the components.

View solution in original post

DCM.jpg
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Visitor
Visitor
5,548 Views
Registered: ‎07-07-2009

Thanks a lot, llewis. Seems it works fine. I remapped input clocks for DCMs (SHIFT_90_1 and SHIFT_90_2) and this errors have gone, but I have a new one:

ERROR:Place:1124 - Unroutable Placement! A BUFGMUX that drives a non-clock load
pin (through the general interconnect) is not placed at a routable site. The
BUFGMUX component <SHIFT_90_1/clkout2_buf> is placed at site <BUFGMUX_X3Y16>.
It drives component <CLK1> on an non-clock load pin. The BUFGMUX can drive
non-clock load pins through general interconnect if the BUFGMUX is in TOP
half of the chip. This placement is UNROUTABLE in PAR and therefore, this
error condition should be fixed in your design. You may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING in order to generate an NCD file. This NCD file can then be used in
FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
clock placement rule is listed below. These examples can be used directly in
the .ucf file to demote this ERROR to a WARNING.
< NET "CLK1" CLOCK_DEDICATED_ROUTE = FALSE; >

 

CLK1 is my clock out pin from SHIFT_90_1 (DCM) and it is mapped to GCLK9 ("P93") (and CLK2 also mapped to clock pin GCLK8 ("P92")) and as I see from your picture it is situated in TOP half of the chip. I can also say that my input clocks SCO1 and SCO2 from ADC channels are also mapped to GCLK11 ("P95") and GCLK10 ("P94"). I have tried to swap these clock pins in different combinations, but have the same result... Please give me one more advice, hove to solve this error.

 

In advance thanks,

Evgenyy.

is in TOP
half of the chip

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Xilinx Employee
Xilinx Employee
5,538 Views
Registered: ‎06-20-2008

The errror message shows that the BUFG is located at site BUFGMUX_X3Y16.  As shown in the new attached picture this is BUFG is in the bottom half of the device.  In Spartan-6 when you use a BUFGMUX to drive NON-Clock loads the BUFG needs to be placed in the top half of the device. 

 

The best way to work around this limitation is to not drive non-clock loads with a BUFG.  To drive a clock off chip you should always use an ODDR register to implement the clock forward.  This will keep the clock on dedicated resources ensuring the fastest lowest skew route and you will not run into the issue you are seeing.

 

To forward the clock just connect the clock to the ODDR CLK pin then tie D1 to GND and D2 to VCC.  This will use the required dedicated resources and will alsways route

Bank2.jpg
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Visitor
Visitor
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Registered: ‎07-07-2009

Thank you, llewis. I will try this. I have also solved this error by placing BUFGMUXs in the top half of device, using LOC constraints in UCF.

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