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Explorer
Explorer
10,212 Views
Registered: ‎07-01-2015

ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi All,

Tool : ISE 14.7,

Board : ML605,

Device : xc6vlx240t -1ff1156

 

  I am working with ML605 board, doing a project with DDR3. Sys_clk and ref_clk are provided by PLL.

So i have changed IBUFGs to BUFG. While implementation i got an error as follows:

 

ERROR:Place:1377 - Regional clock net
"mig_inst/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" is not routable
with loads locked in different clock regions such that it will be impossible
for the source to be routed to all loads. See below for a list of sample
locked components in each clock region. For more information on the clock
region rules, please refer to the architecture user's guide. To debug your
design with partially routed design, please allow mapper/placer to finish the
execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

 

Thanks,

Musthafa 

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1 Solution

Accepted Solutions
Explorer
Explorer
15,341 Views
Registered: ‎07-01-2015

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi All,

 

Finally, the issue is solved. We need to assign proper values for some parameters of MIG. The parameters and its values are given below.

 

nDQS_COL0               = 3,

nDQS_COL1               = 5,

DQS_LOC_COL0            = 24'h020100,

DQS_LOC_COL1            = 40'h0706050403.

 

By doing so errors are solved.

 

Thanks,

Musthafa

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14 Replies
Xilinx Employee
Xilinx Employee
10,206 Views
Registered: ‎02-06-2013

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi

 

Cascaded PLL clock source is not recommended for MIG.

 

It looks you have modified the constraints generated with the core or locked the BUFG to a different clock region which you need to correct.

Regards,

Satish

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Xilinx Employee
Xilinx Employee
10,205 Views
Registered: ‎07-11-2011

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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@musthafavakeri

 

Which IBUFG you have changed and in which file? can you show us the snapshot?

I would suggest to check if you have followed "BUFR Allocation Rules" given in UG406 and reallocate it

 

-Vanitha

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Xilinx Employee
Xilinx Employee
10,199 Views
Registered: ‎09-20-2012

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi @musthafavakeri

 

In case if you have modified the MIG pinout after generating the IP then generate the MIG IP again using "verify ucf and update design" flow where you can load the PRJ and updated UCF file.

Thanks,
Deepika.
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Explorer
Explorer
10,163 Views
Registered: ‎07-01-2015

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi Deepika,

 

I have tried in the way you suggested. But i got an error as follows:

 

ERROR: The same pin was allocated to more than one signal. Check the following:

Pin Name(L15) Signal: ddr3_ba[2]

Pin Name(L15) Signal: sys_clk

 

ERROR:Pins are not unique

 

I haven't mentioned LOC for sys_clk as its connected to the output of PLL. When I go with "create design" flow

no pins are matching for sys_clk. I got errors as "pin has multiple drivers" or the bank of the pin is not matching.

 

Thanks,

Musthafa

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Xilinx Employee
Xilinx Employee
10,159 Views
Registered: ‎07-11-2011

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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@musthafavakeri

 

As teh errors says all ocations constraints should have unique pins 

Can you upload your project here to check the connectivity and errors?

 

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Xilinx Employee
Xilinx Employee
10,158 Views
Registered: ‎09-20-2012

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi @musthafavakeri

 

I see that there are only two options provided for system clock "differential" and "single ended". There is no way to tell the MIG that you are using PLL to generate MIG system clock. This is the reason some pin is being allocated for system clock. See if the UCF file has LOC constraint on sys_clk pin and change it to some other pin to avoid the error.

 

Can't you drive the MIG system clock input from IO directly?

Thanks,
Deepika.
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Explorer
Explorer
10,155 Views
Registered: ‎07-01-2015

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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 Hi Satish,

 

I haven't modified any constraints other than MIG pin assignments.

 

Hi Vanitha,

 

The changes I have done are as follows:

 

1) changed IBUFG to BUFG in clk_ibuf.vhd

 

        se_input_clk : if(INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
-- u_ibufg_sys_clk : IBUFG --this line is commented and added next line
u_ibufg_sys_clk : BUFG
-- generic map(
-- IBUF_LOW_PWR => FALSE
-- )
port map(
I => sys_clk,
O => sys_clk_ibufg
);
end generate se_input_clk;

 

2) commented IBUFG and connected input and output of IBUFG directly in iodelay_ctrl.vhd

 

se_clk_ref: if (INPUT_CLK_TYPE = "SINGLE_ENDED") generate
-- u_ibufg_clk_ref : IBUFG
-- generic map (
-- IBUF_LOW_PWR => FALSE
-- )
-- port map (
-- I => clk_ref,
-- O => clk_ref_ibufg
-- );
end generate se_clk_ref;
--commented IBUFG and added line below
clk_ref_ibufg <= clk_ref;

 

This change is done as it gave error because two buffers are cascaded in this module.

 

Thanks,

Musthafa

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Xilinx Employee
Xilinx Employee
10,153 Views
Registered: ‎07-11-2011

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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@musthafavakeri

 

If you would like to drive the system clock from MMCM and not from external pins,  you need to comment out the IBUF/IBUG in infrastrrcuture module 

 

Instead of going for additional MMCM, If you do not have same clock source as that of memory frequency, follow below AR for the changes 

http://www.xilinx.com/support/answers/35242.html

 

This should work

 

Hope this helps

 

-Vanitha

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Explorer
Explorer
10,149 Views
Registered: ‎07-01-2015

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi Deepika,

 

The oscillators available in the board are

  1) 200 MHz - differential

  2) 66 MHz - single ended.

 

So 200 MHz can be connected to sys_clk. But what about ref_clk...?

 

Thanks,

Deepika

 

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Xilinx Employee
Xilinx Employee
8,554 Views
Registered: ‎07-11-2011

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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200 MHz can be used for system and ref clocks, please check the AR that I posted in my earlier reply

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Explorer
Explorer
8,325 Views
Registered: ‎07-01-2015

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi All,

 

I have tried many ways. But i got same error. So what I did is, I created a sample project of MIG with planahead 14.7

and modified the project as per my requirements. Its working.

 

One of my colleagues told me that ISE gives this error and its better to work in planahead. Is it right ?

 

Thanks,

Musthafa

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Explorer
Explorer
15,342 Views
Registered: ‎07-01-2015

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

Jump to solution

Hi All,

 

Finally, the issue is solved. We need to assign proper values for some parameters of MIG. The parameters and its values are given below.

 

nDQS_COL0               = 3,

nDQS_COL1               = 5,

DQS_LOC_COL0            = 24'h020100,

DQS_LOC_COL1            = 40'h0706050403.

 

By doing so errors are solved.

 

Thanks,

Musthafa

0 Kudos
Explorer
Explorer
7,350 Views
Registered: ‎07-01-2015

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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Hi All,

 

Please note that above parameter values are specific to ML605 Board.

 

Regards,

Musthafa

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Voyager
Voyager
1,826 Views
Registered: ‎10-12-2016

Re: ERROR:Place:1377 - Regional clock net for MIG with DDR3 in ML605 board

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From where i will get these values ?

 

 

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