07-10-2020 01:48 AM
I will need your help.
We actually prepare to move our design from ZC702 eval board to our own hardware (just other package of xc7z020clg):
- change device from ZC702 xc7z020clg484-1 to xc7z020clg400-1
- remove some HDMI input and output IOs and also some logic (should make routing easier)
- change .xdc file and MIO/EMIO with new IO planning
In general we all assumed, that there should be no problem. But anyway, vivado is not able to place the design.
Synthesis Strategy: Flow_AreaOptimized_medium
Implemantation Strategy: Area_Explore
Also tried without any succes:
- set_param place.sliceLegEffortLimit 3000
- control_set_opt_threshold to 16
Does anyone have some advice how to fix this issue?
Thank you very much in advance!
07-10-2020 02:47 AM
The screenshots shown indicate that your design does not fit in the z020clg484. Are you saying that it also does not fit in the z020clg400?
Anyway, the Vivado messages indicate that the number of different “control sets” is making it difficult to efficiently place FFs into the available slices. A control set is the grouping of control signals (set/reset, clock enable and clock) that drives the FF. Reducing the number of different control sets in your design (see page 46 of UG949(v2019.2)) should help.
07-10-2020 03:41 AM
07-10-2020 06:08 AM
What we don't understand is:
Why doses the design fits into z020clg484 and not into z020clg400???
The number of LUTs, Slices, BRAM, DSP, control sets, ... is in both devices the same or not?
07-10-2020 06:25 PM
-just to be clear, your screenshots show the design does NOT fit in the z020clg484. However, I’ll assume (as you say) that you somehow did get the design to fit in the clg484 and not in the clg400 package.
You are correct that the z020clg484 and z020clg400 have the same number of LUTs, FFs, BRAM, and DSP as shown in Xilinx document DS190. However, they may not have the same number of slices.
According to the <this> post, Xilinx sometimes uses the same silicon for different size FPGAs. Vivado will limit the number of FFs and LUTs depending on which FPGA you purchased. However, Vivado will not limit the number of slices. So, although two z020 may be restricted to the same number of FFs and LUTs, they may not be restricted to the same number of slices. Having more slices in which to place the alotted FFs and LUTs means your are not as limited by control sets.
Further, UG865 shows that all banks of the z020clg484 are bonded out. However, bank 33 and part of bank 13 are not bonded out on the z020clg400. So, with the z020clg484 you could use the fabric in bank 33 and then sometimes route directly to IO. However, with the z020clg400, the bank 33 fabric can be used but you must then route back out of bank 33 to reach IO. That is, I suspect that bank 33 usage/routing efficiency is better in the z020clg484 than in the z020clg400.
Anyway, I suggest you use Vivado to try your design in a larger Zynq – like the z030sbg485.
07-12-2020 11:24 PM
First screenshot from error message is from cg400 routing. The overview is from cg484 package, where it fits and works fine on hardware. There are just some failed timings, which need to be fixed.
Thank you for that infomation. There is no bank 33 in cg400 available for placing, but I will check bank 13.