UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer sandeep_sggs
Observer
7,081 Views
Registered: ‎09-11-2008

ERROR_REPORT_HELP

Dear all,

             I am trying to do partial reconfiguration from tcl of ise 9.2. in final phase i m doing the map for top mudule. i get following log with error and the dcr fails. Can anybody pls tell how to get rid of this error:

 

 

% map top.ngd
Release 9.2i - Map J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Using target part "5vlx50ff676-2".
Mapping design into LUTs...
Writing file top.ngm...
Constraining slice packing based on guide NCD.
Constraining slice packing based on guide NCD.
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:9d4411) REAL time: 2 mins 24 secs

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 2 mins 24 secs

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 2 mins 24 secs

Phase 4.33
Phase 4.33 (Checksum:26259fc) REAL time: 2 mins 24 secs

Phase 5.32
Phase 5.32 (Checksum:2faf07b) REAL time: 2 mins 24 secs

Phase 6.2
.....
WARNING:Place:644 - A clock IOB clock component is not placed at an optimal
   clock IOB site. The clock IOB component <clkin_in> is placed at site <AB5>.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.
Phase 6.2 (Checksum:98a237) REAL time: 2 mins 42 secs

Phase 7.30
Phase 7.30 (Checksum:42c1d79) REAL time: 2 mins 42 secs

Phase 8.3
Phase 8.3 (Checksum:4c4b3f8) REAL time: 4 mins 26 secs

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 4 mins 26 secs

Phase 10.8
................................................................
....................................................................................
...............................................................................................................
.................................................................................
...........................................................................
........................
Phase 10.8 (Checksum:13a7248) REAL time: 12 mins 50 secs

Phase 11.29
Phase 11.29 (Checksum:68e7775) REAL time: 12 mins 50 secs

Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 12 mins 51 secs

Phase 13.18
Phase 13.18 (Checksum:7bfa473) REAL time: 17 mins 14 secs

Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 17 mins 15 secs

Phase 16.34
Phase 16.34 (Checksum:98967f0) REAL time: 17 mins 15 secs

REAL time consumed by placer: 17 mins 20 secs
CPU  time consumed by placer: 14 mins 51 secs
Inspecting route info ...
Route info done.
FATAL_ERROR:Pack:pktbamanager.c:1849:1.105.2.5 - Exception during DRC: Illegal
   physical DRC rule operation.   Process will terminate. For more information
   on this error, please consult the Answers Database or open a WebCase with
   this project attached at http://www.xilinx.com/support.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   3
child process exited abnormally

 

 

 

 

 

 

thanks 

sandeep

0 Kudos
4 Replies
Historian
Historian
7,063 Views
Registered: ‎02-25-2008

Re: ERROR_REPORT_HELP

The warning tells you what to do:

 

"WARNING:Place:644 - A clock IOB clock component is not placed at an optimal
   clock IOB site. The clock IOB component <clkin_in> is placed at site <AB5>.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue"

 

So:

 

a) do NOT set that environment variable.

b) Put the clock on a proper clock I/O site (correct pin).

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Observer sandeep_sggs
Observer
7,049 Views
Registered: ‎09-11-2008

Re: ERROR_REPORT_HELP

Hi bassman59,

 

                        Is there any other remedy to get rid of that error ? can u tell if there is any......

 

 

 

sandeep

   

0 Kudos
Historian
Historian
7,000 Views
Registered: ‎02-25-2008

Re: ERROR_REPORT_HELP


sandeep_sggs wrote:

Hi bassman59,

 

                        Is there any other remedy to get rid of that error ? can u tell if there is any......

 

   


 

I'm sorry if you don't like my answer. The only other remedy is to simply not use the tools.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Observer sandeep_sggs
Observer
6,886 Views
Registered: ‎09-11-2008

Re: ERROR_REPORT_HELP

  Hi bassman59,

                          

                                 It's  not  a matter of  likes and dislikes.  And i did't  want to hurt, u if at all i did. U  r expert  and i asked whatever i felt.

 

 

 

 

Regrds,

Sandeep

Message Edited by sandeep_sggs on 03-01-2009 11:16 PM
0 Kudos