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Voyager
Voyager
762 Views
Registered: ‎04-11-2016

ERROR: [Vivado_Tcl 4-130] Power Optimization encountered an error

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Hi,

I saw this thread already:

https://forums.xilinx.com/t5/Implementation/Adding-Chipscope-causes-ERROR-Common-17-70-Application-Exception/td-p/686665

but it didn't solve the issue.

I ended up with following:

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
ERROR: [Pwropt 34-195] Power optimization encountered an error: 'ERROR: [Common 17-70] Application Exception: LUT with more than 6 inputs
'. Skipped power optimization.
Resolution: An unexpected error occurred. For technical support on this issue, please visit http://www.xilinx.com/support. Disable power optimization and rerun implementation to bypass this error.
ERROR: [Vivado_Tcl 4-130] Power Optimization encountered an error.
Ending Power Optimization Task | Checksum: c7094a16

 

Is there any more info about this?

 

 

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Voyager
Voyager
629 Views
Registered: ‎04-11-2016

@hongh
I follow following procedure to get rid of it:
1.generated post-synthesis-dcp
2. opened it
3. created debug core there
4. then run opt, place, route and bitstream manually on tcl console step by step.

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6 Replies
Xilinx Employee
Xilinx Employee
752 Views
Registered: ‎05-22-2018

Hi @fpgalearner ,

I guess there is a edif file in your design which is generated in 3rd party tool?

If yes then either please try to convert the edif file into verilog netilst and check whether it helps.

Thanks,

Raj

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Voyager
Voyager
721 Views
Registered: ‎04-11-2016
@rshekhaw
there is no edif file from third party in the design.
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Moderator
Moderator
697 Views
Registered: ‎11-04-2010

Hi, @fpgalearner ,

The issue your reported is similar to a known issue. 

Could you provide more information about your design?

Device; Vivado version; Operating System

If you can send out your synthesized DCP, I'll help to check whether it's a new issue.

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Voyager
Voyager
679 Views
Registered: ‎04-11-2016

@hongh
Device: xcvu3p-ffvc1517-1-e
Vivado version: 2018.2
operating system: Centos Release 6.9 (Final), kernel Linux 2.6.32-754.12.1el6.x86_64, GNOME 2.28.2
I have to ask if it is allowed to share on forum then let you know.

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Moderator
Moderator
649 Views
Registered: ‎11-04-2010

Hi, @fpgalearner ,

Please try the below opt_design option:

opt_design -retarget -propconst -sweep -verbose

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Voyager
Voyager
630 Views
Registered: ‎04-11-2016

@hongh
I follow following procedure to get rid of it:
1.generated post-synthesis-dcp
2. opened it
3. created debug core there
4. then run opt, place, route and bitstream manually on tcl console step by step.

View solution in original post

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