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Visitor djnik1362
Visitor
2,073 Views
Registered: ‎07-03-2013

Effect of connecting an internal net to an output pin

hi

I am working on a design using Xilinx ISE 12.1 and Spartan 6 LX45 with Verilog.

My design works but some random errors had been traced during test .

I find out that when i connect an internal net to an output pin these

random errors disappear too .

 

Whats wrong ?!

 

Thanks for your support.

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1 Reply
Xilinx Employee
Xilinx Employee
2,069 Views
Registered: ‎07-01-2008

Re: Effect of connecting an internal net to an output pin

It sounds like you have unconstrained paths and the change you made had a random effect that improved the timing on those paths.

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