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Error [Place 30-51] IDELAYCTRL elements have been found to be associated with IODELAY_GROUP 'XX_iodelay_grp1', but the design does not contain IODELAY elements associated with this IODELAY

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Hi Deepika,

I have the same error, I use Vivado 2018.3, device: ZCU106 Board.

I added 5 IP cores: AXI 1G/2.5G Ethernet Subsystem for 2 SFP + 1 SGMII + 2 RGMII interface, 1G. When I try to implement my design I receive this error:

1/
ERROR:


[DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells 'pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i' and
'pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i' have same IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp' but their RST signals are different

2/ I add constrain:
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]


set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

 

Critical warning:


[DRC PLIDC-2] IDELAYCTRLs assigned to group with no IODELAYs: IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY cells associated with this IODELAY_GROUP.


ERROR:


[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rxc_ibuf_i/O] >

pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rxc_ibuf_i/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X2Y240
pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/bufg_rgmii_rx_clk (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X1Y94
pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/bufg_rgmii_rx_clk_iddr (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X1Y122

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/bufg_rgmii_rx_clk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X1Y94

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/bufg_rgmii_rx_clk_iddr (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X1Y122

3/ I add constrain:


set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rxc_ibuf_i/O]


Critical warning:


[DRC PLIDC-2] IDELAYCTRLs assigned to group with no IODELAYs: IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY cells associated with this IODELAY_GROUP.


ERROR:


[Place 30-51] IDELAYCTRL elements have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY elements associated with this IODELAY_GROUP.


3/ command out tri_mode_ethernet_mac_iodelay_grp1


set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

 

#set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rxc_ibuf_i/O]

 

ERROR: the same step 1


[DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells 'pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i' and 'pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i' have same IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp' but their RST signals are different

 

Would you please help me to fix them,

Thank you very much~,

Phuc Le 

 

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Registered: ‎11-04-2010

Hi, @phuc.le.lsi ,

It looks to be a long story after checking your design and I will try to simplify the situation:

For critical warning:

[DRC PLIDC-2] IDELAYCTRLs assigned to group with no IODELAYs: IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY cells associated with this IODELAY_GROUP.

You only set IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1' for IDELAYCTRL cell, but there is no IDELAYE3 cells included inIODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', which causes the CW.

To workaround the situation, you need to add the related IDELAYE3 cell into the IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1'

Example commands:

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells -hier -filter {NAME =~ pl_eth_1g_i/axi_eth_rgmii_1/* && REF_NAME =~ *DELAYE3*}]

But the below error will occurs:

ERROR: [Place 30-803] Clock region X2Y4 has 2 IODELAY_GROUPs, either due to locked IO-Delay elements or due to locked IdelayCtrls. List of groups in this clock region:

Since both groups of IODELAY cells are placed in the clock region_X2Y4, you have to combine these 2 IODELAY_GROUPs and only one IDELAYCTRL can be used .
Check your schematic, the driver registers of 2 RST pins of 2 IDELAYCTRL are different:

pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_support_resets_i/idelayctrl_reset_reg
pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_support_resets_i/idelayctrl_reset_reg

Until now you have 2 choice:

1. Only use one IODELAY_GROUP and one IDELAYCTRL.

2. Move all the I/ODELAYE3 of one IODELAY_GROUP to another clock region. (It will affect the pin planing of your design, NOT recommended).

For method one, you only need to remove one IDELAYCTRL and use one IODELAY_GROUP.

Example commands for you:

open_checkpoint XX_opt.dcp

reset_property IODELAY_GROUP [get_cells -hier -filter {IODELAY_GROUP =~ tri_mode_ethernet_mac_iodelay_grp* }]
remove_cell pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i
place_design

 

 

 

 

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Registered: ‎11-04-2010

The IDELAYCTRLs in the same  IODELAY_GROUP should have the same connection.

Please open the synthesized design and compare the conection of these two IDELAYCTRLs: (RST pin is mentioned in the error message)

select_object [get_clells pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

F4

select_object [get_clells pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

F4

If you cannot make them have the same connection, you have to use the different IODELAY_GROUPs.

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Hi Hongh,

I am a new bie in the Vivado tool.

Please be detailed in your guide.

in design, AXI clock and AXI reset are the same input, the other signals are independent.

 

Thank you very much~

Phuc Le

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Registered: ‎08-09-2019

I use Vivado 2018.3, device: ZCU106 Board.

I added 2 IP cores: AXI 1G/2.5G Ethernet Subsystem for RGMII interface, 1G.

I create constrains for IODELAY_GROUPs:
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

 

Critical warning:


[DRC PLIDC-2] IDELAYCTRLs assigned to group with no IODELAYs: IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY cells associated with this IODELAY_GROUP.

 

Would you please help me to fix them,

Thank you very much~

Phuc Le

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Registered: ‎11-04-2010

[DRC PLIDC-2] 

Please also add IODELAY cells into the IODELAY_GROUP you defined:

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells your_IODELAY_cell_name]

You need to find the your IODELAY cell name in the netlist first.

Steps:

1. Open the synthesized design

2. Ctrl+F

3. Search IODELAY cell and get the full name of these cells.

 

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Open the synthesized design and  Search IODELAY cell.

Result from search IODELAY

Cell name:  IDELAYCTRL 

Name:

-  pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i

pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i

Cell pin count: 3

 

I think that IODELAY_cell_name is true in constrains:

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]


set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]

 

Critical warning:


[DRC PLIDC-2] IDELAYCTRLs assigned to group with no IODELAYs: IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY cells associated with this IODELAY_GROUP.

 

If I have any misunderstand, please kindly help me.

Thank you very much~

 

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IDELAYCTRL should work with IODELAY, and do you mean there is no IODELAY existing in your design?

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I don't use any SelectIO Wizard IP.

I use 2 IP cores: AXI 1G/2.5G Ethernet Subsystem for RGMII interface, 1G in the design.

If I don't add any constrain, ERROR from implementation:

[DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells 'pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i' and
'pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i' have same IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp' but their RST signals are different

 

if I add constrain, re-run synthesis and implementation

Critical warning:


[DRC PLIDC-2] IDELAYCTRLs assigned to group with no IODELAYs: IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY cells associated with this IODELAY_GROUP.

 

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Hi, @phuc.le.lsi ,

It looks to be a long story after checking your design and I will try to simplify the situation:

For critical warning:

[DRC PLIDC-2] IDELAYCTRLs assigned to group with no IODELAYs: IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', but the design does not contain IODELAY cells associated with this IODELAY_GROUP.

You only set IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1' for IDELAYCTRL cell, but there is no IDELAYE3 cells included inIODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1', which causes the CW.

To workaround the situation, you need to add the related IDELAYE3 cell into the IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp1'

Example commands:

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells -hier -filter {NAME =~ pl_eth_1g_i/axi_eth_rgmii_1/* && REF_NAME =~ *DELAYE3*}]

But the below error will occurs:

ERROR: [Place 30-803] Clock region X2Y4 has 2 IODELAY_GROUPs, either due to locked IO-Delay elements or due to locked IdelayCtrls. List of groups in this clock region:

Since both groups of IODELAY cells are placed in the clock region_X2Y4, you have to combine these 2 IODELAY_GROUPs and only one IDELAYCTRL can be used .
Check your schematic, the driver registers of 2 RST pins of 2 IDELAYCTRL are different:

pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_support_resets_i/idelayctrl_reset_reg
pl_eth_1g_i/axi_eth_rgmii_1/inst/mac/inst/tri_mode_ethernet_mac_support_resets_i/idelayctrl_reset_reg

Until now you have 2 choice:

1. Only use one IODELAY_GROUP and one IDELAYCTRL.

2. Move all the I/ODELAYE3 of one IODELAY_GROUP to another clock region. (It will affect the pin planing of your design, NOT recommended).

For method one, you only need to remove one IDELAYCTRL and use one IODELAY_GROUP.

Example commands for you:

open_checkpoint XX_opt.dcp

reset_property IODELAY_GROUP [get_cells -hier -filter {IODELAY_GROUP =~ tri_mode_ethernet_mac_iodelay_grp* }]
remove_cell pl_eth_1g_i/axi_eth_rgmii_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i
place_design

 

 

 

 

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Hi @hongh 

 

Thank you for your guidance,

Our team have fixed these Errors,

 

Phuc Le

 

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