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Visitor pitawask
Visitor
12,469 Views
Registered: ‎01-18-2009

Error during NGDBuild

 Hi,

 

I'm using ISE 6.2 and writing my FPGA code in Verilog. This is a circuit for a simple CPU and get the following error message in translating phase. Can someone please tell me what this means. Compiling and synthesis is completed with no errors. 

 

------------------------------------- 

 

Error message:

 

Checking timing specifications ...

Checking expanded design ...

ERROR:NgdBuild :605 - logical root block 'CPU_S' with type 'CPU_S' is unexpanded.

Symbol 'CPU_S' is not supported in target 'spartan3'.


NGDBUILD Design Results Summary:
 
Number of errors:     1
Number of warnings:   0
Total memory usage is 38128 kilobyte
One or more errors were found during NGDBUILD. 
No NGD file will be written.

 

--------------------------------------

 

Thanks.

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5 Replies
Xilinx Employee
Xilinx Employee
12,456 Views
Registered: ‎08-13-2007

Re: Error during NGDBuild

It means you are using a module called CPU_S that isn't resolved and isn't a device primitive when it runs ngdbuild.

The likely cause is either:

-this module is RTL source and you haven't synthesized it so it is a black box

-this is a netlist and ngdbuild can't find it:

http://www.xilinx.com/support/answers/11701.htm (Project Navigator - Translation fails on design with CORE Generator macros: "ERROR:NGDBuild:604 - Logical block 'xxxxx' with type 'xxxxx' is unexpanded")

bt

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Visitor pitawask
Visitor
12,446 Views
Registered: ‎01-18-2009

Re: Error during NGDBuild

Thanks, Compiling and synthesis was completed without any problem. I tried the translate properties tab but no success so far.

 

Do you see anything wrong with my code or possible reasons for this error.

 

Thanks,

 

 

------------------------------------------

 module CPU_S(clock, run);
  
input clock, run;
reg [3:0] pc, ir, mar, mbr, dreg, mbr_out;
reg fetch_complete, mem_write;
wire clock, run;
wire [3:0] mbr_in;

main_mem mm1 (.clk(clock),.add_in(mar),.data_out(mbr_in),.data_in(mbr_out),
    .rd_wr(mem_write));

always @(posedge clock)
begin
if (run)
case (fetch_complete)
1'b1 :
 begin
 ir[1:0] = mbr[3:2];
 mar[1:0] = mbr[1:0];
 case (ir)
  4'bxx00 : begin mem_write =0; mbr = mbr_in; dreg = mbr;  end // load
 4'bxx01 : begin mem_write =0; mbr = mbr_in; dreg = dreg + mbr; end // add
 4'bxx10 : begin mem_write =0; mbr = mbr_in; dreg = dreg - mbr ;end // subtract
 4'bxx11 : begin mbr = dreg; mbr_out = mbr; mem_write = 1;  end// store
 endcase
 end
1'b0 :
    begin
 mem_write=0;
 mar = pc;
 mbr= mbr_in;
 pc=pc+1;
 fetch_complete =1;
 end
endcase
end 
endmodule

module main_mem (clk, add_in, data_out, data_in, rd_wr);

input add_in, data_in, clk, rd_wr;
output data_out;
wire [3:0] add_in, data_in;
reg [3:0] data_out;
reg[3:0] membyte[0:16];
wire rd_wr;

always@(posedge clk)
begin
if(rd_wr)
membyte[add_in]= data_in;
else
data_out = membyte[add_in];
end
endmodule
------------------------------------------------

 

Thanks.

 

Message Edited by pitawask on 02-16-2009 01:20 PM
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Xilinx Employee
Xilinx Employee
12,430 Views
Registered: ‎08-13-2007

Re: Error during NGDBuild

For future reference, just because a step completed without errors doesn't mean there isn't problems. For example, instantiating a module as a black box may result in a warning in synthesis but you'll get an error in ngdbuild if it can't find the netlist. It is always a good practice to review the warnings from the previous step(s) if you are having issues.

 

In this case, assuming this is your only level of hierarchy, I would:

-make sure I/O buffers are being inferred (XST properties, Xilinx Specific options -> Add I/O buffers)

-review any warning from the synthesis log file.

 

bt

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Xilinx Employee
Xilinx Employee
12,427 Views
Registered: ‎08-13-2007

Re: Error during NGDBuild

Ok, I quickly ran your design in 10.1.03i:

It passes ngdbuild but fails map:

ERROR:Map:116 - The design is empty.  No processing will be done.

 

The problem is your design only has 2 inputs: clock and run.

There are no outputs so the entire design gets optimized away.

 

There may be a slight difference in 6.2 in terms of the optimization (where this occurs), but with no output - the design really can't do anything.

I suspect you meant to have some of these signals as outputs.

 

bt

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Visitor pitawask
Visitor
12,381 Views
Registered: ‎01-18-2009

Re: Error during NGDBuild

Thnaks so much for doing this. I didn't have any outputs: I thought I would use a stimulus block to monitor the memory location where the result is stored.

I will add an output and re run this, Thanks again.

 

 

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