02-23-2016 01:02 AM
I am implementing a design in verilog using Xilinx ISE 14.7 using primitive instantiation based approach. An example of instantiating a LUT is as follows:
.INIT(64'h0000CC5A000000AA) // Specify LUT Contents
) LUT6_2_inst0 (
.O6(sel), // 1-bit LUT6 output
.O5(d0), // 1-bit lower LUT5 output
.I0(ud), // 1-bit LUT input
.I1(ext), // 1-bit LUT input
.I2(ff), // 1-bit LUT input
.I3(ld), // 1-bit LUT input
.I4(1'b0), // 1-bit LUT input
.I5(1'b1) // 1-bit LUT input (fast MUX select only available to O6 output)
However, on checking the implemented LUT in Xilinx FPGA editor, it may be seen that Xilinx ISE is not preserving the input ordering to the physical LUT pins. On applying LOCK_PINS constraint as (* LOCK_PINS = “all” *), it is giving design errors. I want to retain the ordering of inputs as specified in the HDL. How should I understand a valid input ordering?
02-23-2016 02:52 AM - edited 02-23-2016 02:57 AM
What is the error you see when you use LOCK_PINS constraint?
Instead of using ALL attribute use PIN assignment list as mentioned in page-158 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf
02-24-2016 02:24 AM
I am synthezing a 4-bit counter using a primitive instantiation based approach along with a constrained placement (placement constraints are mentioned in the .ucf) of the primitives on the FPGA fabric. The .v files and .ucf files are appended for your reference.
When I am providing the (* LOCK_PINS = “all” *) constraints in the .v file without the.ucf file the "Implement Design" is running successfully but is inferring more hardware than expected.
However, when I am providing the .ucf and retaining the LOCK PINS constraint it is giving an error as follows:
Directed packing was unable to obey the user design constraints (LOC=SLICE_X0Y1) which requires the combination of the symbols listed below to be packed into a single SLICEL component.
Retaining the placement constraints is crucial for my design. Also retaining the input ordering of signals to the physical LUT pins must be deterministic, which I am unable to achieve.
02-24-2016 08:51 PM
The complete error report is as follows:
The directed pack was not possible because: The function generators were
found to have incompatible input signals.
The symbols involved are:
LUT symbol "LUT6_2_inst1/LUT5" (Output Signal = d0<1>)
LUT symbol "LUT6_2_inst1/LUT6" (Output Signal = sel<1>)
LUT symbol "LUT6_2_inst2/LUT5" (Output Signal = d0<2>)
LUT symbol "LUT6_2_inst2/LUT6" (Output Signal = sel<2>)
Carry symbol "CARRY4_inst0" (Output Signal = cc<0>)
FLOP symbol "FDRE_inst0" (Output Signal = q_0_OBUF)
FLOP symbol "FDRE_inst1" (Output Signal = q_1_OBUF)
LUT symbol "LUT6_2_inst3/LUT5" (Output Signal = d0<3>)
FLOP symbol "FDRE_inst2" (Output Signal = q_2_OBUF)
LUT symbol "LUT6_2_inst3/LUT6" (Output Signal = sel<3>)
FLOP symbol "FDRE_inst3" (Output Signal = q_3_OBUF)
LUT symbol "LUT6_2_inst0/LUT5" (Output Signal = d0<0>)
LUT symbol "LUT6_2_inst0/LUT6" (Output Signal = sel<0>)