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Visitor
Visitor
9,523 Views
Registered: ‎07-23-2015

Event counter in verilog

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hi,

i'm a verilog beginner, i'm try to write a "event counter" on verilog.... this is my code, but it work only with "period" set to 16'b0000000000000001, if try set period to 16'b0000000000001000, result(out_event) is always '0'. Someone can help me to fix it ?

 

module mymodule(
    input  wire          clk,
    input  wire             enable,
    input  wire             reset, 
    input    wire [15:0]        period,
    input    wire              in_event, 
    output reg                  out_event            
);

reg en = 1'b0; 
reg re = 1'b0;
reg [15:0] count = 16'b0000000000000000;
always @(posedge clk) en <= enable;
always @(posedge clk) re <= reset;


always @(in_event)begin


if(in_event == 1'b1)begin
if(re)begin
    count <= 0 ; 
    out_event <= 1'b0;
end else begin
    if(en) begin
        if(count == period-1)begin
            out_event <= 1'b1;
            count <= 0;
        end else begin
            count <=count + 1;
            out_event <= 1'b0;
        end
    end else begin
        out_event <= 1'b0;
    end
end

end else begin
    out_event <= 1'b0;

end

end 

endmodule

thanks in advance

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Highlighted
Teacher
Teacher
17,398 Views
Registered: ‎03-31-2012
you need to sample the in_event only at a clock edge so instead of always @(in_event), you need always @(posedge clk) too:
always @(posedge clk) begin
if (reset)
count <= 0;
out_event <= 0;
else
...
count <= count + 1;

etc.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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4 Replies
Highlighted
Teacher
Teacher
17,399 Views
Registered: ‎03-31-2012
you need to sample the in_event only at a clock edge so instead of always @(in_event), you need always @(posedge clk) too:
always @(posedge clk) begin
if (reset)
count <= 0;
out_event <= 0;
else
...
count <= count + 1;

etc.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

Highlighted
Moderator
Moderator
9,501 Views
Registered: ‎07-01-2015

Hi @marco_mion,

 

I am attaching the verilog code and testbench which is working for period 16'b0000000000001000.

I am attaching the snapshot of the testbench also.

 

Thanks and Regards,
Arpan

 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
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Highlighted
Moderator
Moderator
9,474 Views
Registered: ‎07-01-2015

Hi @marco_mion,

 

Please mark the Answer as "Accept as solution" if information provided is helpful.

 

Thanks and Regards,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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Highlighted
Visitor
Visitor
9,458 Views
Registered: ‎07-23-2015
Hi, thanks Arpan for your help, my code work only in simulation but when synthesizes it did not work. I have solved rewriting all the code with.... always @(posedge clk) begin ...
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