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Visitor sgehrer
Visitor
8,038 Views
Registered: ‎08-28-2013

FIXED_ROUTE not working on Zynq

Hi,

 

I'm trying to get the FIXED_ROUTE property in Vivado 2013.2 to work. It's working fine on Artix/Kintex/Virtex devices. But when using a Zynq device, the P&R stops after "Phase 1.4 Routing Based Site Exclusion" without any more information. The error message only says "Implementation failed" and nothing more.

 

I tried different designs and locations on the Zynq, but can't get it to work (although its working fine on non-Zynq devices). I also used set_property for the LOC/BEL/PINS to restrain him as much as possible.

 

As soon as i remove the fixed_route property the P&R works fine and even uses the routing I try to restrain.

 

Regards,

Stefan

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7 Replies
Xilinx Employee
Xilinx Employee
8,023 Views
Registered: ‎04-16-2012

Re: FIXED_ROUTE not working on Zynq

Hi,

 

Can you share the runme.log located in impl_1 folder?

Also share the xdc constraint you are using?

 

Thanks

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Visitor sgehrer
Visitor
8,009 Views
Registered: ‎08-28-2013

Re: FIXED_ROUTE not working on Zynq

sure thing! the runme.log:

 

 

*** Running vivado
    with args -log RO.rdi -applog -m64 -messageDb vivado.pb -mode batch -source RO.tcl -notrace


****** Vivado v2013.2 (64-bit)
  **** Build 272601 by xbuild on Sat Jun 15 11:27:26 MDT 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: Implementation
INFO: [Common 17-81] Feature available: Implementation
INFO: [Common 17-78] Attempting to get a license: Synthesis
INFO: [Common 17-81] Feature available: Synthesis
INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/Vivado/2013.2/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.2/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.2/data/parts/xilinx/rtl/prims/rtl_prims.xml]
INFO: [Common 17-362] Using Tcl App repository from 'C:/Xilinx/Vivado/2013.2/data/XilinxTclStore'.
INFO: [Common 17-364] Updating Tcl app persistent manifest 'C:/Users/abc/AppData/Roaming/Xilinx/Vivado/tclapp/manifest.tcl'
source RO.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2013.2
Loading clock regions from C:/Xilinx/Vivado/2013.2/data\parts/xilinx/zynq/zynq/xc7z020/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2013.2/data\parts/xilinx/zynq/zynq/xc7z020/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2013.2/data\parts/xilinx/zynq/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2013.2/data\parts/xilinx/zynq/zynq/xc7z020/clg484/Package.xml
Loading io standards from C:/Xilinx/Vivado/2013.2/data\./parts/xilinx/zynq/IOStandards.xml
INFO: [Opt 31-138] Pushed 1 inverter(s).
INFO: [Common 17-78] Attempting to get a license: Internal_bitstream
WARNING: [Common 17-301] Failed to get a license: Internal_bitstream
Parsing XDC File [D:/Xilinx_Projects/test_fixed_routing/test_fixed_routing.srcs/constrs_2/new/constraint.xdc]
Finished Parsing XDC File [D:/Xilinx_Projects/test_fixed_routing/test_fixed_routing.srcs/constrs_2/new/constraint.xdc]
Parsing XDC File [D:/Xilinx_Projects/test_fixed_routing/test_fixed_routing.srcs/constrs_2/new/constraint_impl.xdc]
Finished Parsing XDC File [D:/Xilinx_Projects/test_fixed_routing/test_fixed_routing.srcs/constrs_2/new/constraint_impl.xdc]
Parsing XDC File [D:/Xilinx_Projects/test_fixed_routing/test_fixed_routing.runs/impl_1/.Xil/Vivado-xxx/dcp/RO.xdc]
Finished Parsing XDC File [D:/Xilinx_Projects/test_fixed_routing/test_fixed_routing.runs/impl_1/.Xil/Vivado-xxx/dcp/RO.xdc]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Phase 0 | Netlist Checksum: 5091c045
link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 685.160 ; gain = 540.980
Command: opt_design
INFO: [Common 17-347] Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 688.773 ; gain = 3.508

Starting Logic Optimization Task
Logic Optimization | Checksum: cdbcc6b3
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 1 Retarget

INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: b7c930e5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 689.953 ; gain = 1.145

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-10] Eliminated 0 cells.
Phase 2 Constant Propagation | Checksum: b7c930e5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 690.105 ; gain = 1.297

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 0 unconnected nets.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 3 Sweep | Checksum: b7c930e5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 690.219 ; gain = 1.410
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: b7c930e5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 690.297 ; gain = 1.488

Starting Power Optimization Task
Ending Power Optimization Task | Checksum: b7c930e5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 690.418 ; gain = 0.121
20 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.107 . Memory (MB): peak = 691.598 ; gain = 0.668
Command: place_design
INFO: [Common 17-347] Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 695.375 ; gain = 0.000

Phase 1.1 Mandatory Logic Optimization
INFO: [Opt 31-138] Pushed 0 inverter(s).
Phase 1.1 Mandatory Logic Optimization | Checksum: 7d2b066e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 695.375 ; gain = 0.000

Phase 1.2 Build Super Logic Region (SLR) Database
Phase 1.2 Build Super Logic Region (SLR) Database | Checksum: 7d2b066e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 695.699 ; gain = 0.324

Phase 1.3 Add Constraints
Phase 1.3 Add Constraints | Checksum: 7d2b066e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 695.699 ; gain = 0.324

Phase 1.4 Routing Based Site Exclusion

 and the constraints:

 

set_property LOC SLICE_X0Y0 [get_cells i1_inferred_i_1]
set_property BEL A6LUT [get_cells i1_inferred_i_1]
set_property LOC SLICE_X0Y0 [get_cells i2_inferred_i_1]
set_property BEL B6LUT [get_cells i2_inferred_i_1]
set_property LOC SLICE_X0Y0 [get_cells i3_inferred_i_1]
set_property BEL C6LUT [get_cells i3_inferred_i_1]

set_property LOCK_PINS {I0:A6 I1:A3} [get_cells i1_inferred_i_1]
set_property LOCK_PINS {I0:A5} [get_cells i2_inferred_i_1]
set_property LOCK_PINS {I0:A6} [get_cells i3_inferred_i_1]

set_property FIXED_ROUTE { { CLBLM_M_A CLBLM_LOGIC_OUTS12 IMUX_L24 CLBLM_M_B5 }  } [get_nets i1]
set_property FIXED_ROUTE { { CLBLM_M_B CLBLM_LOGIC_OUTS13 IMUX_L35 CLBLM_M_C6 }  } [get_nets i2]

 

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Community Manager
Community Manager
7,989 Views
Registered: ‎06-14-2012

Re: FIXED_ROUTE not working on Zynq

If its a hang, then this is not the right way. Will it be possible to send the project for further investigation. 

I can send you the ezmove link. 

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Visitor sgehrer
Visitor
7,982 Views
Registered: ‎08-28-2013

Re: FIXED_ROUTE not working on Zynq

sure thats possible

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Community Manager
Community Manager
7,963 Views
Registered: ‎06-14-2012

Re: FIXED_ROUTE not working on Zynq

I have sent the ezmove link to you. Please send the project to reproduce the issue

 

Regards

Sikta

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Xilinx Employee
Xilinx Employee
7,945 Views
Registered: ‎07-01-2008

Re: FIXED_ROUTE not working on Zynq

A case came in that confirms that fixed_route constraints don't work in 2013.2. The problem is fixed already for 2013.3.

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Xilinx Employee
Xilinx Employee
7,927 Views
Registered: ‎09-20-2012

Re: FIXED_ROUTE not working on Zynq

Hi Stefan,

 

I have checked the test case which you have sent in relation to this forum thread. This design works fine in vivado 2013.3 too. 

 

Vivado 2013.3 is tentatively scheduled to be released by october end.

 

Thanks,

Deepika.

Thanks,
Deepika.
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