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Participant sum@
Participant
86 Views
Registered: ‎02-06-2019

FPGA Arty A7 board

My code was running properly in simulation .As i have to provide input externally their is no output expected.When i run implementation it is showing error as

  • [Place 30-494] The design is empty Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
  • [Common 17-69] Command failed: Placer could not place all instances
Capt33ure.JPG
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Moderator
Moderator
70 Views
Registered: ‎11-04-2010

Re: FPGA Arty A7 board

Hi, sum@ ,

This thread is replicated to the below one:

https://forums.xilinx.com/t5/Implementation/implementation-in-verilog-vivado/td-p/982783

Please avoid posting the same question in the different threads.

 

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