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Explorer
Explorer
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Registered: ‎05-21-2009

FPGA editor bistream generation limitation

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Hi guys,

 

Just a quick question. Is there a limitation on FPGA editor to generate a bitstream for a design containing an embedded processor, such as a PowerPC? The reason I am asking is because I've created a design in Project Navigator and ran the PAR. I then opened the placed and routed design in FPGA editor and tried to create the bitstream from there. However, I simply receive an error the bitstream couldn't be generated. No other reason was given. 

 

I am using ISE 14.7 and a Virtex-5 FPGA. 

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Explorer
Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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I apologize for the delay in response. I ran into some other non-related issues with the project and only recently solved the problem I had in this thread.


Apparently the issue originated from "edkBmmFile.bmm" that was required from the Top Level design, before the bitstream could be generated. After saving the ncd to the new location and copying "edkBmmFile.bmm" to the same location, the bitstream was succesfully generated. I stumbled upon this when trying to generate the same bitstream from command line. The error was much clearer.

View solution in original post

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Scholar
Scholar
13,592 Views
Registered: ‎02-27-2008

Re: FPGA editor bistream generation limitation

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r,

 

Is the device targeted a FX device?

 

Which one?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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Hi Austin,

 

The device is a VFX70T.

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: FPGA editor bistream generation limitation

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What is the exact error?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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I just want to clarify the ISE is able to create the bitstream without any errors.

 

I have saved the routed ncd-file from a project in a different directory. If I open that in FPGa editor, I simply get an error: "The bitgen command failed to write the .bit file." That's it. No other errors or warnings.

 

Considering that ISE is capable of generating the bitstream, and if FPGA editor has no limitation on creating the bitream for a project containing an embedded processor, I would think some other file (or something) is required with the ncd-file before the bitstream can be created. Am I correct in my assumption?

 

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Scholar
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Registered: ‎02-27-2008

Re: FPGA editor bistream generation limitation

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r,

 

The ncd file should contain everything required for FPGA_Editor to create a bit or bin file.

 

There may be data that goews into BRAM which is in .bmm files, so for it to work, you may need more files, but to create a bitstream, they are not required.  To create a bitstream that ctually works and does what you want, you will need the BRAM content files, if BRAM are used in your design.

 

Are you specifying a valid name for the bitfile? (check that the name has characters that are allowed to be used in a name).

 

Can you open FPGA_Editor, do nothing at all, write a (empty) ncd file, go back and read in that ncd file, and write a bitstream?  Even though it is empty, it should create a valid bitstream, that may be downloaded to the device (DONE will go high) and it will fo nothing else.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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Hi Austin,

 

I tried creating the an empty ncd in the same directory as the one the failing, and the bitsream was sucessfully created. So I tried a couple of different things.

 

I reopened the original design in ISE and reopened the routed design in FPGA editor from here. I then saved the ncd file to a different directory and immediately tried creating the bitstream, which completed successfully. However, If I close everything and open the ncd file in FPGA editor, bitgen fails.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: FPGA editor bistream generation limitation

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Hi,

 

In the ncd that is failing, can you run DRC in FPGA Editor --> Tools --> DRC --> Run and see if there are any warnings?

 

--Hem

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Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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Hi Hem,

 

If I run DRC, I have 1156 warnings and 0 errors. The warnings are mostly pins not driving any load in the design. However, I don't think that is what's causing the issues. If I open FPGA editor from ISE, save the design, run DRC and then generate the bitstream, I get exactly the same amount of warnings and the bitstream is generated.

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Scholar
Scholar
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Registered: ‎06-14-2012

Re: FPGA editor bistream generation limitation

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Hi

If I understand the issue correctly, bitstream is generated succesfully when you are invoking FPGA editor from ISE .

 

If you use the same ncd thats generated in par directory and then load in FPGA EDITOR STANDLONE, it fails,

Are you using to write or save the ncd from FPGA editor?

 

Regards

Sikta

 

 

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Explorer
Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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Hi Sikta,

 

Yes, that is indeed the case. Eventually I would like to make some changes in FPGA editor, but for now, I only open the ncd and click on bitgen.

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Scholar
Scholar
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Registered: ‎06-14-2012

Re: FPGA editor bistream generation limitation

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Hi,

I was just able to reproduce this with a example BIST design. The problem is due to the other options for bitgen.

Just remove them from the window. If you want to override your bit file, just have -w and then you should be able to generate bitstream succesfully through FED.

 

Adding the screenshot for your reference. Hope this helps.

 

Regards

Sikta

 

 

Capture.PNG
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Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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Thanks for the effort Sikta! Much appreciate it. However, I don't have other bitgen options. I guess there is something else I am missing.

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Scholar
Scholar
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Registered: ‎06-14-2012

Re: FPGA editor bistream generation limitation

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Opened FED with placed and routed ncd , pcf and changed the mode to read and write. I am running this in ISE 14.7.

 

Regards

Sikta

 

 

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Scholar
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Registered: ‎06-14-2012

Re: FPGA editor bistream generation limitation

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Explorer
Explorer
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Registered: ‎05-21-2009

Re: FPGA editor bistream generation limitation

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I apologize for the delay in response. I ran into some other non-related issues with the project and only recently solved the problem I had in this thread.


Apparently the issue originated from "edkBmmFile.bmm" that was required from the Top Level design, before the bitstream could be generated. After saving the ncd to the new location and copying "edkBmmFile.bmm" to the same location, the bitstream was succesfully generated. I stumbled upon this when trying to generate the same bitstream from command line. The error was much clearer.

View solution in original post

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