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Visitor
Visitor
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Registered: ‎07-23-2020

Failed Implementation: Spartan 6 to Spartan 7 Migration

Errors:

[Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.

[Common 17-69] Command failed: Placer could not place all instances

Warning messages:

[Vivado 12-584] No ports matched 'TOP_LB'. 

[Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

Above are the two errors that caused the failure along with some of the top warning messages. I have all of the pins assigned in an xdc file based on locations in an Orcad schematic. Do I need to also assign them in Vivado? I do not how to reconcile the two, or even how to read the schematics in Vivado properly. There are leaf cells still there, they were not removed. What does it mean to make sure everything is instantiated? Does this refers again to the pin assignments in the XDC file? 

If you have any other thoughts or suggestions to resolve the issue, please let me know and I can try to address it.

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4 Replies
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276 Views
Registered: ‎06-21-2017

Look in your hierarchy/sources tab.  Is it showing the correct top level entity?  Look through the hierarchy.  Is anything missing?  Is the correct constraints file listed in the source tab?  Open the synthesized design and then open the synthesized schematic.  Do you see your ports?  Does anything connect your input ports to your output ports?

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Visitor
Visitor
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Registered: ‎07-23-2020

I am not sure what the top level entity should be. There are several unit test bench files. I went ahead and updated it to one of the '..._tb' regarding main.v, but I will check with my team lead to confirm. I have the physical constraints xdc file added, but I am still working on converting the timing ucf to xdc format. Could that cause the error? I see some ports, but not in the same way that I do in the schematic in OrCad.
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233 Views
Registered: ‎06-21-2017

A test bench should not be the top level entity for synthesis.

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Visitor
Visitor
174 Views
Registered: ‎07-23-2020

I was able to navigate down a level, and set the main.v as the top module for both the design sources and the simulation sources. This prompted a synthesis failure due to outdated IP Core instantiations, which after those were fixed, both the synthesis and implementation builds have completed successfully. Thank you for your assistance with this issue.
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