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Adventurer
Adventurer
237 Views
Registered: ‎10-14-2017

Failed timing when regenrating project with tcl script

Hello,

I have a project which has a block design and uses various Xilinx IP cores and also has my own VHDL written cores integrated into the block design. I synthesized and implemented the deisgn ad ran it on my dev board just fine. No problems with timing whatsoever. However, when I then re-generated project from tcl script (file-> project->write tcl..) and tried implementing it, the design fails timing and reports setup violation. What is even weirder is that failing nets are not my written, but are associated with PS7 core. I thought that re-genrating project with tcl script generates an identical project to the original one with all the same settings. So how can this be and how can I resolve this issue?

The nets that are failing are as follows:

image.png

5 Replies
Moderator
Moderator
180 Views
Registered: ‎03-16-2017

Re: Failed timing when regenrating project with tcl script

Hi @ronnu,

1. Are you migrating from one Vivado version to others?  If yes, then which versions. 

2. Provide the steps which you used to regenerate the project through tcl script. 

3. Check the warnings and critical warnings that were not present earlier with the original project. 

4. Compare that timing critical path with both original project and regenerated project and provide the difference. 

5. Provide the timing report to evaluate after implementation. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Xilinx Employee
Xilinx Employee
153 Views
Registered: ‎05-08-2012

Re: Failed timing when regenrating project with tcl script

Hi @ronnu 

A side by side comparison of the synthesis and implementation reports should show where they diverge.


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Adventurer
Adventurer
140 Views
Registered: ‎10-14-2017

Re: Failed timing when regenrating project with tcl script

Hi @hemangd 

Thank you for the reply and sorry for my late answer! I'm on travels now so cannot answer all your questions right away, but:

1. No I'm using Vivado 2018.3 on both the original project and on the regenerated project.

2. I selected "File->Project->Write tcl.." and then selected "Write all properties", "Copy sources to new project", "Recreate block design using Tcl", "Write object values". After Vivado had generated the project I manually modified the tcl file to select the directory where the project is generated. I then closed the project and ran the tcl script to generate the project.

As for your other questions, I will do those when I get the chance and post the results here.

Thank you!

 

 

 

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Adventurer
Adventurer
136 Views
Registered: ‎10-14-2017

Re: Failed timing when regenrating project with tcl script

Yes, I think there were a lot more warning generated with the new project compared to the old project. I will check those warnings when I get back and post results here.

Thank you!

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Adventurer
Adventurer
72 Views
Registered: ‎10-14-2017

Re: Failed timing when regenrating project with tcl script

Hi,

Sorry for the big delay. I was on a vacation and forbidden to go anywhere near my computer :D

Anyways, I have now tried some things. I tried doing a comparisment of warnings in the original project and in the regenerated projects. There were a lot of new warnings in the regenerated projects, but nothing seemed to be showing what caused this problem. I can share the list of warning in both projects if needed.

However it seems that I did manage to solve the problem. When trying to regenerate the project again, I un-checked the "Write all properties" and "Write object values" radio buttons when generating Tcl script. After I regenerated the project using this new tcl script, implementation was completed without any timing violations being reported. I do not know what difference these should make, but they solve the problem.

Is this logical? What is actually meant under properties and object values? I thought it's properties of all the IP core that are instantiated in the block design.

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