cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
397 Views
Registered: ‎05-04-2020

Failed to place design-DSP overutilization

Jump to solution

I am trying to generate the bitstream for a project and I get this error:

 

Implementation
Place Design
[Place 30-859] Some DSP area constraints are over utilized.

18 or more DSP failed to place. The unplaced DSP are constrained as below: (listing maximum of 20 DSPs per constraint)
Area constraint: Tool:Shape
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[15].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[19].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[61].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[11].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[13].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[9].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[58].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[59].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[60].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[26].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[28].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[62].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[63].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[57].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
Tile rectangles examined:
Rect: ((0, 155), (579, 310))

  Number of DSP required by this constraint: 2368
  Number of DSP available in this constraint region: 1380
  Utilization = 171%

Area constraint: Tool:Shape
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[56].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[36].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[33].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
  ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[52].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg
Tile rectangles examined:
Rect: ((0, 466), (579, 621))

  Number of DSP required by this constraint: 1731
  Number of DSP available in this constraint region: 1380
  Number of DSP blocked in this constraint region: 14
  Utilization = 125%



[Place 30-99] Placer failed with error: 'The following macros could not be placed:
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[11].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[13].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[15].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[19].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[26].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[28].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[33].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[36].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[52].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[56].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[57].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[58].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[59].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[60].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[61].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[62].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[63].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
<MSGMETA::BEGIN::BLOCK>ku115_i/cl_wrapper_0/inst/u_bf_wrap/sys_array/LOOP_INPUT_FORWARD[9].LOOP_OUTPUT_FORWARD[0].pe_inst/reg_inst/out_reg_reg/DSP_ALU_INST<MSGMETA::END> (DSP_ALU)
The total BRAM utilization is 93.31, the total DSP utilization is 603.3 and the total URAM utilization is 0
A possible reason is high utilization of BRAMs, DSPs, URAMs, or RPMs. Please check user constraints to make sure design is not over-utilized in the constraint areas (if any) keeping in mind some macros require a number of consecutively available sites
'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

 

 I am generating the bitstream for KCU1500 and the project has been done for KCU1500 before, So I assume I am doing something wrong or there should be a way to resolve this problem. I would appreciate if anyone has any idea how can resolve this. 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
187 Views
Registered: ‎01-05-2017

Re: Failed to place design-DSP overutilization

Jump to solution

Hi @nzh ,

After some internal consultation here a better option would be to run opt_design excluding retarget. This is should allow the placer to complete. Can you try this and let us know if it works?

The command is:

opt_design -sweep -propconst -bram_power_opt

Best Regards.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

6 Replies
Highlighted
Xilinx Employee
Xilinx Employee
326 Views
Registered: ‎01-05-2017

Re: Failed to place design-DSP overutilization

Jump to solution

Hi @nzh ,

Could you upload the post_opt DCP and I will take a look.

Best Regards.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
281 Views
Registered: ‎05-04-2020

Re: Failed to place design-DSP overutilization

Jump to solution

@dsheils Thank you for the help, I uploaded the dcp file here:

https://drive.google.com/open?id=1dvd4UwRddfxKCwbLaXqkcWI86Ul35HXL

The original project/code can also be found here in this project on github

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎01-05-2017

Re: Failed to place design-DSP overutilization

Jump to solution

Hi @nzh 

Can you set the following in the TCL Console and rerun implementation. Let me know if it works.

set_param logicopt.enableDSPCascadeFixing false

 Regards.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
188 Views
Registered: ‎01-05-2017

Re: Failed to place design-DSP overutilization

Jump to solution

Hi @nzh ,

After some internal consultation here a better option would be to run opt_design excluding retarget. This is should allow the placer to complete. Can you try this and let us know if it works?

The command is:

opt_design -sweep -propconst -bram_power_opt

Best Regards.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

Highlighted
Moderator
Moderator
128 Views
Registered: ‎01-16-2013

Re: Failed to place design-DSP overutilization

Jump to solution

@nzh 

 

Can you update us back on this thread? If the information provided above by @dsheils was helpful then please mark his post as "Accept as solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
87 Views
Registered: ‎05-04-2020

Re: Failed to place design-DSP overutilization

Jump to solution

@syedz @dsheils it's successfully implemented now. 

0 Kudos