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Registered: ‎08-04-2018

Failing timing closure when slightly changing design

Hey there!

I'm building a design based on the code for the USRP X310, by Ettus Research. The timing itself is pretty constrained, and I've never seen a WNS greater than 16 ps when the timing closes as intended (using a frequency of around 200 MHz for a large portion of the core).

The thing is, I've seen that very small changes in my design, sometimes not even logic related (new comments or changing registers' names) occasionally cause my next (synthesis and) implementation to fail at timing closure, usually by very small margins (sub 100 ns for WNS; btw this might sound stupid but I usually re-implement the design even though I changed no functionality just because I hate it when Vivado tells me the project is out-of-date).

For my implementation strategy I use phys_opt_design both after place and route, and the directives are set to Explore or AggressiveExplore wherever possible.

I had the idea that Vivado was deterministic about the results of implementation, and in these cases I'm confident the synthesis process should yield identical results. What can I do to get more consistent results?

Thanks in advance!

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Registered: ‎11-04-2010

Re: Failing timing closure when slightly changing design

Hi, @pollo_vignolo ,

 You can try the incremental flow described in UG904.

Don't forget to reply, kudo, and accept as solution.
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