Failing timing constraint error

[hirailyassahi]

i am using xilinx 14.7 and KC705. while implmentation i get timing constraint error

The code is 

module lfsr (data,
out , // Output of the counter
enable , // Enable for counter
clk_p , // clock input
clk_n,
reset // reset input
);

//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
input [7:0] data;
input enable, clk_p,clk_n, reset;
//------------Internal Variables--------
reg [7:0] out;
wire clk;
wire linear_feedback;

IBUFGDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
) IBUFGDS_inst (
.O(clk), // Clock buffer output
.I(clk_p), // Diff_p clock buffer input
.IB(clk_n) // Diff_n clock buffer input
);

//-------------Code Starts Here-------
assign linear_feedback = !(out[7] ^ out[3]);

always @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (enable) begin
out <= {out[6],out[5],
out[4],out[3],
out[2],out[1],
out[0], linear_feedback};
end
endmodule

UCF file

NET "enable" LOC = Y29 | IOSTANDARD = "LVCMOS25";
NET "reset" LOC = AB12 | IOSTANDARD = "LVCMOS15";
NET "clk_n" LOC = AD11 | IOSTANDARD = "LVDS";
NET "clk_p" LOC = AD12 | IOSTANDARD = "LVDS";
NET "out<0>" LOC = AB8 | IOSTANDARD = "LVCMOS15";
NET "out<1>" LOC = AA8 | IOSTANDARD = "LVCMOS15";
NET "out<2>" LOC = AC9 | IOSTANDARD = "LVCMOS15";
NET "out<3>" LOC = AB9 | IOSTANDARD = "LVCMOS15";
NET "out<4>" LOC = AE26 | IOSTANDARD = "LVCMOS25";
NET "out<5>" LOC = G19 | IOSTANDARD = "LVCMOS25";
NET "out<6>" LOC = E18 | IOSTANDARD = "LVCMOS25";
NET "out<7>" LOC = F16 | IOSTANDARD = "LVCMOS25";

Error

[syedz]

@hirailyassahi,

This is not an error but a warning that your design doesnt contain any timing constraints. 

You need to apply PERIOD constraint in the UCF which is the basic timing constraint. Please check page number 192 in below UG:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgd.pdf

--Syed

[arpansur · Accepted solution]

Hi @hirailyassahi,

As you are using sysclk for clock

For KC705 sysclk frequency is 200MHz. You will get the same information in page-27 of following link:

http://www.xilinx.com/support/documentation/boards_and_kits/kc705/ug810_KC705_Eval_Bd.pdf

You have to add equivalent constraints in the ucf.

NET "clk_p" TNM_NET = clk_p;
TIMESPEC TS_clk_p = PERIOD "clk_p" 5 ns HIGH 50%;

Thanks,
Arpan

[hirailyassahi]

so for this code it will be like this?

Net clk_n PERIOD = 20000 ps;

Net clk_p PERIOD = 20000 ps;

[syedz]

@hirailyassahi,

adding to above Arpan post since your requirement is 20000 ps.

Please use :

NET "clk_p" TNM_NET = clk_p;
TIMESPEC TS_clk_p = PERIOD "clk_p" 20 ns HIGH 50%;

You can also use constraint editor (Tools-->Constraint Editor) which will help you in writing proper UCF timing constraints.

--Syed

[hirailyassahi]

i have to do this for clk_n also?

[arpansur]

Hi @hirailyassahi,

If you apply for only clk_p, it will be propagated to clk_n also. So no need of constraining clk_n too.

Thanks,
Arpan