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Adventurer
Adventurer
464 Views
Registered: ‎01-09-2018

Failure in warnings potentially causing device damages?

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1. The warnings do not detect errors such as a wire connected the wrong side, and the synthesis simply stops with a red error and no explanation.

1(a) The legacy tools such as ISE42 gave me the warnings and I managed to fix the misconnected wire. anyone else with warning failures in vivado? why is that that ISE detects and reports errors and Vivado simply omits to give any information?

2. When making my design too big to fit it just gives an error and no indication of how much % I exceeded in that size.

2(a) With ISE42 it exeeds its ability to handle memory

2(b) With quartus it indicates how much % overshoot in size

I really need to have the informations is there any settings to unmute those warnings or a place to go look at? I need to use other tools or prior versions to do that but am suspecting that Vivado must have that information somewhere and I am just missing out where exactly

3. When implementing the exact design but doubling the size, it shows the same FF % and LUT % utilisation, is the tool keeping track accurately of the utilisation, anyone having this experience?

4. I tried reset_project to re run all and hope the messages appear, it seems that they where muted due to a "too large number" (obviously if they always repeat the warning for each repeated instance).

Is there a way to force warnings to only show what is not redundant or repeated and not mute the rest?

Is there a special synthesis/implementation setting for very large logic designs?

CAUTION: this may cause chip damages for the following situations:

4:55AM PST [case No.1] On a simple test with a swtitch to led situation I just tested a node that was unstable and unclocked so it could not be metastable I thought, the equations had an error and it was a combinational loop (same as a circle reference in excel) so the poor drivers where swtiching on on one end and off the other and drawn all the current. When my finger got near the switch the electrostatic seemed to then have affected the result that when out of the metastability I observed?

[improvement request No. 1] Vivado failed to give a warning on that but even in excel it gives a warning for the circle reference situation, would that not be something important 

I had in the past situations with latch inference and if based on similar errors could cause the same short circuit situation?

Anyone experiencing those issues:

- ESD noise on a switch input

- short circuit due to logic undetected error ( assign A = B; assign B = ESD noise || A;) 

- short circuit due to logic seeping through a misfortunately inferred latch

I just experienced an ESD interfering with the outcome of internal unclocked logic circuits, that had a "sort circuit loop" undetected error, could I have damaged my FPGA ?

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Xilinx Employee
Xilinx Employee
409 Views
Registered: ‎05-08-2012

Re: Failure in warnings potentially causing device damages?

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Hi @xlyns 

I would suggest having separate posts for different topics, as they might need to be viewed on separate Forums boards.

For the synthesis messaging, I would suggest veiwing the log file either under the reports tab (bottom of Vivado), or within a project it can be found at "<project_name>.runs/<run_name>/runme.log" This would have the relavent information about errors.

To find the current design utilization, I would open the Synthesized Design and enter "report_utilization". This is also available when implementation is run under the reports tab.

The Vivado IDE Guide has more information on the Reports tab and the Messaging window.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug893-vivado-ide.pdf#page=121

I beleive you are also asking about the messaging limit. This can be increased with the following paramter. The following will only not print messages after 100,000 of the same message ID are printed.

set_param messaging.defaultLimit 100000


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Don’t forget to reply, kudo, and accept as solution.
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Don’t forget to reply, kudo, and accept as solution.
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3 Replies
Xilinx Employee
Xilinx Employee
410 Views
Registered: ‎05-08-2012

Re: Failure in warnings potentially causing device damages?

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Hi @xlyns 

I would suggest having separate posts for different topics, as they might need to be viewed on separate Forums boards.

For the synthesis messaging, I would suggest veiwing the log file either under the reports tab (bottom of Vivado), or within a project it can be found at "<project_name>.runs/<run_name>/runme.log" This would have the relavent information about errors.

To find the current design utilization, I would open the Synthesized Design and enter "report_utilization". This is also available when implementation is run under the reports tab.

The Vivado IDE Guide has more information on the Reports tab and the Messaging window.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug893-vivado-ide.pdf#page=121

I beleive you are also asking about the messaging limit. This can be increased with the following paramter. The following will only not print messages after 100,000 of the same message ID are printed.

set_param messaging.defaultLimit 100000


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

 

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
Adventurer
Adventurer
395 Views
Registered: ‎01-09-2018

Re: Failure in warnings potentially causing device damages?

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I am glad we can use TCL to do that thansk for guiding me i'll use it great!

here a more private reply I got and it seems relevant

"I'm sorry to hear you are having issues - but what you describe here sounds like things that may be caught by liniting tools. FPGA synthesis and elaboration can also catch some coding errors, but for example latch inferral is not an error / or wont damage a device - it may be intended.  It sounds like you are requesting Vivado to warn about these constructs. Have you provided some code-examples illustraitng each of the issues. Feature requests or debugging can only be done when there is a concrete example that can be reproduced (i.e. verilog example file / part / tool-version / etc). From what you described so far I don't see anything as device damaging. even the input/output connected backwards - its impossible internally to have the drive direction incorrect, so at the worst case the connection would be dropped. It sould be noted that I've seen may other verilog tools / simulators ignore the port direction of input and output and instead just look at the connectivity of driver/receivers, as an input or output is a 'guide' in the module definitin, The actual function depends on how the related signal is used within the sending and receving modules. However, I agree a warning would be useful in this case though."

I replied:

"I know that latch inference can drain clock currents in some situations, specially where combinational loops are then caused by signals coming to early or too late, I am not totally sure so I might be talking over my head but it is what would explaing that LED diode going off then. The synthesis tools also block on latch inference without giving any reason, they just go out of processing memory and fail. It would be great to help the designers with something telling them if a wire is upside down or if there is a loop in its logic or a latch, it used to be automatically listed in ISE warnings."

I hope the TCL tells me that the input is wrongly connected to an output and detects inferred latches and loops, those are errors that can also cause the synthesis tool to err in circles and fail in timeout I noticed. The ISE used to do that so I am missing my ISE warnings and used to use them to create my designs, my way around is to generate my code using javascript (avoiding typo errors and spending hours or having to use the block design that cannot handle busses) and ISE42 or the latest Intel Quartus for information on common errors (Loop, IO directions, Latrches etc..)

I just hope Xilinx could give that back at least because we had it in ISE, I also wonder if Vivado could try become a bit more"reverse compatible" to ISE or have a task force to try and get those details fixed.

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Adventurer
Adventurer
283 Views
Registered: ‎01-09-2018

Re: Failure in warnings potentially causing device damages?

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I have my fist Loop error message so the error messages now seem to work again ??:

 

[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is design_1_i/AApads_0/inst/down2_1[6]. Please evaluate your design. The cells in the loop are: design_1_i/AApads_0/inst/rollover[1][0]_i_2.

 

this is amazing news in no previous versions did vivado even notice that and here it did so something is progressing it seems -

just wanted to thanks whoever has fixed the error messageing for the loops I used to open a Quartus project and see the Intel/altera messages and even use ISE4.2 because both work, but now I am so glad that Vivado picks it up so my design implementation speed is better I am so grateful

 

 

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