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Registered: ‎03-26-2010

Fatal Error in Map - invalid merge operation detected

Hi all,


I'm using ISE 14.1 with patch, targeting a Virtex-5. In my design there is a classic double-FF clock domain crossing circuit, and I wanted to constrain the path between the two different clock domains, i.e. output FF of the first domain, and input of the FF for first of two FFs of the second domain. I've got logic optimization and register retiming turned on, effort at high-normal, all other optimiziations turned off.


As soon as physical synthesis turns on, Map errors out with the following message:

FATAL_ERROR:Timing:DoodleSubExperiment.c:872:1.35 - Invalid merge operation detected: 0x0 -> 0xfefefeff     Process will terminate.

 What is this?! This was not happening before I added the constraint... Without logic optimization this works fine and above error is not seen.


Besides, what kind of source file name is DoodleSubExperiment.c anyway???

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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎07-01-2008

Re: Fatal Error in Map - invalid merge operation detected

This error hasn't been reported before so there's not much I can say about root cause except to say that all fatal errors are bugs. The term "doodle" is used internally for temporary data structures used by applications. This particular module is only mentioned in one CR (for an issue unrelated to this) so it normally manages to stay out of trouble. Physical Synthesis is a post placement resynthesis of the design. You might be able to avoid the error by applying either "S" properties to the FFs invovled or "KEEP" properties to their output nets in order to block any optimizations from occurring. I'm not sure which Physical Synthesis is more likely to respond to.

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