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iafo1
Visitor
Visitor
3,485 Views
Registered: ‎02-05-2010

Fatal error during mapping of ddr2 logic

Map report this error:

 

FATAL_ERROR:MapLib:basmmfrag.c:1718:1.45 - pin D on frag
   DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u
   _iob_dqs/u_tri_state_dqs cannot be toggled.   Process will terminate. For
   technical support on this issue, please open a WebCase with this project
   attached at http://www.xilinx.com/support.

 

To solve it I have to disable "retiming" option of global optimization...actually I'd like to let retiming option enabled.

What can I do? Thanks

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2 Replies
sarithas
Xilinx Employee
Xilinx Employee
3,484 Views
Registered: ‎08-23-2008

can you try applying a 'SAVE' constraint on the signal DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_tri_state_dqs, and with global opt option.

 

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bwade
Scholar
Scholar
3,463 Views
Registered: ‎07-01-2008

We've seen this error code is a similar but different circumstance. As near as I can tell, the mapper tried incorrectly to push an inversion onto a non-invertible pin. That's where the "cannot be toggled" part of the message comes from. Maybe a KEEP constraint on the net driving the D pin of the DDR2 will block the inverter push.  An "S" property on the DDR2 instance may also help.

 

NET "some_net_name" KEEP;

or

INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_tri_state_dqs" S;

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