09-10-2013 05:54 AM
I am working on a VHDL design and after Place and Route, I need to know all signals that pass through a circular area around a chosen point on the FPGA.
So I began to parse XDL and XDLRC files to try to locate all signals of my design but it became quite a tough task considering my design.
I wanted to know if there is any solution for that using Xilinx tools (I am not very familiar with Xilinx environment), maybe PlanAhead could do that ? Or any command that provides me files easier to parse ? In XDL files, all tiles are given in coordinates on the FPGA, is there a way to convert these information in metric unit according to a specific device ?
Thanks in advance for your suggestions !
09-10-2013 11:50 AM
FPGA Editor is the ISE tool that allows you to examine the details of routing resource utilization. It has scripting features but I don't really see how you could get what you want except as a manual process. Vivado on the other hand allows you to make TCL calls to querry the information you need. Vivado only supports 7-series or later devices.
09-11-2013 12:09 AM
Thank you very much for your answer.
So I am going to introduce me to FPGA Editor and I will see what I can do with it.
09-11-2013 02:34 AM
Do you know if FPGA Editor and PlanAhead work with all Xilinx FPGA families (for both newer and older) ?
09-11-2013 05:21 AM
Which families are we talking here? Do you mean all?
FPGA Editor is a older but powerful tool. That should have support to all families.
Planahead will not have support for all older families.The oldest ones that it has support will include Virtex-II,Virtex-II Pro (X),Spartan-3 and Virtex-4.
09-11-2013 09:56 AM
FPGA Editor supports all device supported by ISE except for the CPLDs. For some of tje really old devices you would need to use an old legacy toolset.
09-13-2013 09:19 AM
Thank you both !
So I begin to be a little bit more familiar with FPGA Editor and I have an other question concerning the signal research.
I observed that all signals are not displayed in the List window in FPGA Editor, for example I have a bus of 128 bits in my design declared as std_ulogic_vector but only 36 bits (non-consecutive) are displayed. So since FPGA Editor works on NCD files, I checked if these signals were also missing in the XDL file and this is actually the case. For example, for the bus "factor", I can find in XDL file :
inst "adder_inst/factor<3>" "SLICEX",placed CLEXL_X15Y129 SLICE_X24Y129
inst "adder_inst/factor<7>" "SLICEX",placed CLEXL_X15Y130 SLICE_X24Y130
but not : factor<0>, factor<1>, factor<2>, factor<4>, factor<5>, factor<6>, factor<8> and so on...
I have added the attribute "keep" on all the signals to match the name in the PAR netlist and my VHDL files but that does not seem to be enough to keep all signals. Does my problem come from VHDL files or is it in optimization rules during Place And Route ?
09-13-2013 09:53 AM
Assuming that the signals exist post-synthesis, one of several things may have happened:
1. They were trimmed as unused. Check trim report in .mrp file. Use "S" property in UCF file to block trimming.
2. They were optimized to constant. Use "S" property in UCF file to block optimization.
3. They were entirely absorbed into component. Use "KEEP" in UCF file to prevent this.
4. They were optimized away by one of the re-synthesis options. Turn off these options.