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Observer ibrahimsangi
Observer
680 Views
Registered: ‎01-24-2019

Four MIPI CSI-2 Rx IPs error in implementation

Hi all,

I am using Ultra96 and with that I am using four MIPI CSI-2 IP blocks. I am getting an error in implementation of it. The error is unable to place IO clock in clock regions. I am getting this error when I use "Shared Logic Included in Core"

But when I use " Include Shared Logic in example design". I am not getting any error. The hardware gets through each step pretty good.

while, I am not getting anything in frame write buffers from slaves MIPI CSI-2 IPs

 

  • [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

 

I did connections according to below pdf page no. 33.

https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v3_0/pg232-mipi-csi2-rx.pdf

mipi.PNG

Can anyone please explain where the problem is if I am not wrong D-Phy is unable to get the clock...

 

Thank you have a nice day.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Four MIPI CSI-2 Rx IPs error in implementation

Hi @ibrahimsangi 

 

Can the log file be attached after adding the -verbose option to place_design? The error is suggesting to review the log for Critical Warnings or Warnings that could lead to this message, so it would be helpful to review.


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Moderator
Moderator
637 Views
Registered: ‎11-09-2015

Re: Four MIPI CSI-2 Rx IPs error in implementation

HI @ibrahimsangi ,

I am confused. You said you did the connections following the pg232 but you are using "Shared Logic Included in Core"?

It does not make sense because the connections are done for "Include Shared Logic in example design", this is when the slave cores include pll_lock_in...

Anyway, it is expected that you cannot fit multiple MIPI CSI-2 RX IPs in the same IO bank if you are not using "Include Shared Logic in example design" for all except one which remain master as you will not have enough clocking ressources.

You need to share the clocking ressources between the core and this is why you need to use "Include Shared Logic in example design" in 3 of 4 IPs. In the 4th one you need to use "Shared Logic Included in Core" to include the clocking ressources (PLL) in the master core.

Then, we would need to debug why you are not getting any data out from the slave IPs. But I would suggest you start by following the debugging section of pg232

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer ibrahimsangi
Observer
629 Views
Registered: ‎01-24-2019

Re: Four MIPI CSI-2 Rx IPs error in implementation

Thank you for the reply Marcb

Please find attached runtime log files. And let me know if you need anything else.

 

Thank you

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Observer ibrahimsangi
Observer
626 Views
Registered: ‎01-24-2019

Re: Four MIPI CSI-2 Rx IPs error in implementation

Thank you Florentw.

I can easily put two MIPI CSI-2 RX IP with "Shared Logic Included in Core" and these two are working fine. I am getting photos from it via yavta.

Here is what currently working and what is not

1) MIPI_RX -------- Shared Logic Included in Core ------------------ working

2) MIPI_RX -------- Shared Logic Included in Core ------------------ working

3) MIPI_RX -------- Include Shared Logic in example design ----- I can see pipline is being recognized by petalinux but Yavta command waits for buffers to be filled by data

4) MIPI_RX -------- Include Shared Logic in example design----- I can see pipline is being recognized by petalinux but Yavta command waits for buffers to be filled by data

I can see all piplines being probed successfully. One more issue that I am not sure of is I am using petalinux 2018.3 and vivado 2018.3. And Vivado uses MIPI CSI-2 IP v4.0 so, when I go to device tree to bind it on v4.0. I am unable to probe MIPI CSI-2 in the kernel logs.

Please let me know about this. I think I am not getting clock on the slave RX and I have no idea why?

Thank you.

 

 

 

 

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Moderator
Moderator
616 Views
Registered: ‎11-09-2015

Re: Four MIPI CSI-2 Rx IPs error in implementation


@ibrahimsangi wrote:

Thank you Florentw.

I can easily put two MIPI CSI-2 RX IP with "Shared Logic Included in Core" and these two are working fine. I am getting photos from it via yavta.

Here is what currently working and what is not

1) MIPI_RX -------- Shared Logic Included in Core ------------------ working

2) MIPI_RX -------- Shared Logic Included in Core ------------------ working

3) MIPI_RX -------- Include Shared Logic in example design ----- I can see pipline is being recognized by petalinux but Yavta command waits for buffers to be filled by data

4) MIPI_RX -------- Include Shared Logic in example design----- I can see pipline is being recognized by petalinux but Yavta command waits for buffers to be filled by data

I can see all piplines being probed successfully. One more issue that I am not sure of is I am using petalinux 2018.3 and vivado 2018.3. And Vivado uses MIPI CSI-2 IP v4.0 so, when I go to device tree to bind it on v4.0. I am unable to probe MIPI CSI-2 in the kernel logs.

Please let me know about this. I think I am not getting clock on the slave RX and I have no idea why?

[Florent] - I do not understand what you mean here... vivado 2018.3 uses the MIPI CSI-2 RX v4.0 so this is the expected version of the driver

Thank you.

 


[Florent]- Can you share a register dump of the non-working IP. It would be useful if the D-PHY register are also available (need to be enabled in the IP configuration)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer ibrahimsangi
Observer
610 Views
Registered: ‎01-24-2019

Re: Four MIPI CSI-2 Rx IPs error in implementation

@florentw 

[Florent] - I do not understand what you mean here... vivado 2018.3 uses the MIPI CSI-2 RX v4.0 so this is the expected version of the driver

When I bind device tree with

compatible = "xlnx,mipi-csi2-rx-subsystem-4.0"

I am not getting anything in kernel log like this one. (below are logs when I bind with compatible = "xlnx,mipi-csi2-rx-subsystem-3.0" )

[ 1.429557] xilinx-csi2rxss b0000000.mipi_csi2_rx_subsystem: Xilinx CSI2 Rx Subsystem device found!
[ 1.429720] xilinx-csi2rxss b0020000.mipi_csi2_rx_subsystem: Xilinx CSI2 Rx Subsystem device found!
[ 1.429866] xilinx-csi2rxss b0060000.mipi_csi2_rx_subsystem: Xilinx CSI2 Rx Subsystem device found!
[ 1.430010] xilinx-csi2rxss b0080000.mipi_csi2_rx_subsystem: Xilinx CSI2 Rx Subsystem device found!

[Florent]- Can you share a register dump of the non-working IP. It would be useful if the D-PHY register are also available (need to be enabled in the IP configuration)

I have enabled the D-phy interface. How can I get register dumps. Do you know any command for this. I am sorry, I am very new with these FPGA and linux.

 

 

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Observer ibrahimsangi
Observer
609 Views
Registered: ‎01-24-2019

Re: Four MIPI CSI-2 Rx IPs error in implementation

@florentw 

Device tree for CAM1

device.PNG

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Moderator
Moderator
591 Views
Registered: ‎11-09-2015

Re: Four MIPI CSI-2 Rx IPs error in implementation

HI @ibrahimsangi ,

I am not getting anything in kernel log like this one. (below are logs when I bind with compatible = "xlnx,mipi-csi2-rx-subsystem-3.0" )

[Florent] - Ok, I understand now. It seems that this is missing from the 2018.3 tag in the repo. The development team seems to have added it to the master branch. So if needed, you should be able to build from the master branch. But I do not think this will change the behaviour.

I have enabled the D-phy interface. How can I get register dumps. Do you know any command for this. I am sorry, I am very new with these FPGA and linux.

[Florent] - You should be able to read into the registers with devmem


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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