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Visitor laomar
Visitor
176 Views
Registered: ‎05-12-2019

Freeze design in vivado

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hello,

i am working with vivado2018.2".

i made an example of code to initiate 4 LUT and to each lut i attribute a value 

after that i run implementation and i generate bitstream to get ebc file (i saved this one) and i reinitiate the  4 LUTs by their complement i made the implementation and i generated the bitstream and i got a second ebc file.

in result to verify that it is correct when i compare the 2 ebc file i have to get (4*64 =256 bits that changed), but in my case i found 260.

So i need to freeze my design so that if i make any change in my code (initiate LUT) nothing change.

i tried with command lock_design and fix cell with pb block in  floorplannig but nothing happened.

thanks,

this my vhdl code:

library ieee;
use ieee.std_logic_1164.all;
library virtex;

entity lut is
port (
LUT1_IN, LUT2_IN : in std_logic_vector(1 downto 0);
LUT1_OUT, LUT2_OUT : out std_logic_vector(1 downto 0)
);

end entity lut;

architecture XILINX of LUT is

component LUT1

generic (INIT: bit_vector(1 downto 0) := "10");
port (O : out std_logic;
I0 : in std_logic);
end component;

component LUT2

generic (INIT: bit_vector(3 downto 0) := "0000");
port (O : out std_logic;
I0, I1 : in std_logic);
end component;

begin

-- LUT1 used as an inverter


U0 : LUT1 generic map (INIT => "10")

port map (O => LUT1_OUT(0), I0 => LUT1_IN(0));

-- LUT1 used as a buffer

U1 : LUT1 generic map (INIT => "01")

port map (O => LUT1_OUT(1), I0 => LUT1_IN(1));

-- LUT2 used as a 2-input AND gate

U2 : LUT2 generic map (INIT => "0111")

port map (O => LUT2_OUT(0), I1 => LUT2_IN(1), I0 => LUT2_IN(0));

-- LUT2 used as a 2-input NAND gate

U3 : LUT2 generic map (INIT => "1000")

port map (O => LUT2_OUT(1), I1 => LUT2_IN(1), I0 => LUT2_IN(0));

end XILINX;

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1 Solution

Accepted Solutions
Moderator
Moderator
85 Views
Registered: ‎11-04-2010

Re: Freeze design in vivado

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You can apply dont_touch property with the wild card.

Ex: 

set_property dont_touch true [get_cells -hier -filter {REF_NAME=~ LUT*}]

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6 Replies
Moderator
Moderator
144 Views
Registered: ‎11-04-2010

Re: Freeze design in vivado

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Hi, @laomar ,

If you just intend to modify the initial value of a LUT in your design without any change of other part of the design, you can open the routed.dcp and modify the INIT property of the target LUT directly.

Ex: set_property INIT 4'h6 [get_cells LUT_instance_name]

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Visitor laomar
Visitor
128 Views
Registered: ‎05-12-2019

Re: Freeze design in vivado

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hi @hongh ,

thanks for your answer.

i do what u said and i modified my xdc file but always i found 260Bits as difference between the two ebc file.

 

 

 

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Visitor laomar
Visitor
116 Views
Registered: ‎05-12-2019

Re: Freeze design in vivado

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hey,
i just added
set_property DONT_TOUCH TRUE [get_cells [list U0 U1 U2 U3]] in xdc file and it works now.

thanks,
Mariem
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Moderator
Moderator
105 Views
Registered: ‎11-04-2010

Re: Freeze design in vivado

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Hi, @laomar ,

"dont_touch" property helps the avoid optimization for the LUTs, such as LUT combine.

With the set_property command used on the netlist, you can only modify the initial value of LUT without touching any other thing in the design.

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Visitor laomar
Visitor
99 Views
Registered: ‎05-12-2019

Re: Freeze design in vivado

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HI @hongh ,

 

That code was just an example to know how to initiate the 134600 lut of Artix 7: Xilinx part number XC7A200T-1SBG484C .

i am thinking to devide it into 8 part each part contain 16825 Luts.

am i  doing right?

in this case how can i use "don't touch" ?

 

 

thanks,

 

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Moderator
Moderator
86 Views
Registered: ‎11-04-2010

Re: Freeze design in vivado

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You can apply dont_touch property with the wild card.

Ex: 

set_property dont_touch true [get_cells -hier -filter {REF_NAME=~ LUT*}]

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------