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Newbie knguyen003
Newbie
857 Views
Registered: ‎09-19-2017

Frequency multiplication

Hello community,

 

The FPGA is XCV812E-6bg560, being built with ISE 9.1.03i.  There is one input clock to the FPGA at 20MHz.  The FPGA is capturing some information to memory.  The new requirement is to increase the resolution, i.e. capturing at a faster rate of 80MHz.  Some data will be captured at the 80MHz and clock domain crossing it to the 20MHz domain via FIFO.  The rest of the data are still captured at 20MHz clock.  So the system needs to run on 2 clocks, 20MHz and 80MHz. There can only be FPGA update.  No modification to the board design.  I approached this design in the following 2 ways.

Design 1:  Global input clock is routed to an IBUFG.  Its output is fed to a clock multiplier circuit to generate a 40MHz clock pulses.  It then is routed to a BUFG and ultimately to CLKIN of DLL.  20MHz FPGA internal clock is the output of the IBUFG.  80MHz FPGA internal clock is DLL CLK2X output.

Design 2:  Same as design (1), except the 20MHz FPGA internal clock is DLL CLKDV output.  80MHz FPGA internal clock is DLL CLK2X output.

 

I obtained the clock multiplier code from one of the Xilinx forums.


Due to design limitation, I can't route the 80MHz output to a testpoint.  I fed the 80MHz to a flop to generate 40MHz clock. This 40MHz clock is routed to a testpoint, along with DLL Lock.  I constraint the LOC of the clock multiplier sites, DLL and BUFG locations, to be the same on both designes.  Probing these test points showed that for design (1), DLL Lock is HIGH and there's 40MHz clock.  For design (2), DLL Lock is HIGH but no 40MHz clock.

Post place and route simulation showed the clock pulses going to the DLL CLKIN are 1.169 ns and 1.531 ns for design (1) and design (2) respectively.  For both designes, simulation shows DLL generates LOCK and CLK2X clocks.

Question 1:  
I couldn't find what's the minimum pulse width requirement for DLL CLKIN.  The 1.169 ns and 1.531 ns shown in post place and route simulation seems to be too short, but I don't know what the minimum requirement is.

Question 2:  
I'd prefer to use design (2), since both the internal 20MHz and 80MHz clocks are from the DLL.  But I couldn't figure out why there's clock in design (1) and not design (2). 

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