UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant kirito0816
Participant
402 Views
Registered: ‎11-26-2018

Get stuck in opt design (phase5 sweep)

Hello,

I am using Vivado 2016.4 to run a axi design. The project was stuck in opt_design, phase5 sweep. I looked at the log file and there is no error. Here are the log file and some warnings. I wonder if there any method to figure out the error or the details of implementation. Thank you.

messages.PNG

0 Kudos
10 Replies
Xilinx Employee
Xilinx Employee
389 Views
Registered: ‎05-22-2018

Re: Get stuck in opt design (phase5 sweep)

Hi @kirito0816 ,

Firstly i will suggest you to migrate to latest Vivado version, if there is no limitation at your end.

And for workaround try removing the sweep option from opt_design phase, check the below AR# link for that:

https://www.xilinx.com/support/answers/53845.html 

Thanks,

Raj

0 Kudos
Moderator
Moderator
378 Views
Registered: ‎01-16-2013

Re: Get stuck in opt design (phase5 sweep)

@kirito0816 

 

How long did you wait to confirm that the tool got stuck during sweep stage? Check timestamp of runme.log file present in impl_1 folder and check if the time is regularly getting update. Also can you share the log file after running with verbose option with opt_design command.

image.png

--Syed 

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Participant kirito0816
Participant
346 Views
Registered: ‎11-26-2018

Re: Get stuck in opt design (phase5 sweep)

I have to use version 2016.4. And I will try to remove the sweep option. It will take 10 hours to see the result. Thank you.
0 Kudos
Participant kirito0816
Participant
342 Views
Registered: ‎11-26-2018

Re: Get stuck in opt design (phase5 sweep)

The timestamp of runme.log is 2019/12/10 0:03 and I post the question at about 9:50am.(about 10 hours) I will try to use this method and post the result. Thank you.
0 Kudos
Xilinx Employee
Xilinx Employee
269 Views
Registered: ‎05-22-2018

Re: Get stuck in opt design (phase5 sweep)

Hi @kirito0816 ,

Does removing sweep option helped to bypass the issue?

Thanks,

Raj

0 Kudos
Participant kirito0816
Participant
236 Views
Registered: ‎11-26-2018

Re: Get stuck in opt design (phase5 sweep)

@rshekhaw
Thank you. There is a little change in opt_design. There is one more message. But it is still in opt_design. I am still waiting.
0 Kudos
Participant kirito0816
Participant
199 Views
Registered: ‎11-26-2018

Re: Get stuck in opt design (phase5 sweep)

@rshekhaw The opt_design passed! And there comes a new error in place_design.
[DRC 23-20] Rule violation (NDRV-1) Driverless Nets - Net pcie0/inst/pcie4_ip_i/inst/pcie_4_0_pipe_inst/pcie_4_0_e4_inst_n_3698 are undriven.
I wonder if this is related with previous option in opt_design? Thank you.
0 Kudos
Xilinx Employee
Xilinx Employee
187 Views
Registered: ‎05-22-2018

Re: Get stuck in opt design (phase5 sweep)

 Hi @kirito0816 ,

After opt_design run the below command to check whether it gives some more information on errors or not.

place_design -nets [get_netspcie0/inst/pcie4_ip_i/inst/pcie_4_0_pipe_inst/pcie_4_0_e4_inst_n_3698]

Thanks,

Raj

0 Kudos
Participant kirito0816
Participant
164 Views
Registered: ‎11-26-2018

Re: Get stuck in opt design (phase5 sweep)

Hi, @rshekhaw

I tried this commend
place_design -nets [get_nets pcie0/inst/pcie4_ip_i/inst/pcie_4_0_pipe_inst/pcie_4_0_e4_inst_n_3698]
but it said that the "-nets"is not an option.
[Common 17-170] Unknown option '-nets', please type 'place_design -help' for usage info.
I tried "place_design -help" and the options are
"-directive <arg>, -no_timing_driven , -timing_summary, -unplace, -post_place_opt, -quiet, -verbose"
Thank you.
0 Kudos
Xilinx Employee
Xilinx Employee
118 Views
Registered: ‎05-22-2018

Re: Get stuck in opt design (phase5 sweep)

Hi @kirito0816 ,

Apologies my bad.

Will it be possible for you to sghre the post opt dcp with us?

Also in opt design device view search for that particular net and check for the proper driver for that net, either it is getting trimmed of or not.

Thanks,

Raj

0 Kudos