Global Logic 0 is getting assigned by design's port and creating 'X' in the PAR simulation model
While generating the PAR simulation model, in design_timesim.v file, I am geeting 1 assignment as
NlwRenamedSignal_GLOBAL_LOGIC0 = Clk_ForceRxmode
After this all other signals are assigned with this signal ( NlwRenamedSignal_GLOBAL_LOGIC0).
Since this signal (NlwRenamedSignal_GLOBAL_LOGIC0) is already the output signal from the output buffer (Xilinx logic0 output buffer). So its becoming the multidriven signal and propagating 'X' through out the design.
The signal Clk_ForceRxmode is assigned to zero in the design.
If any one have any idea on this issue please let me know. This would be a great help. Please let me know if you want to know any more detail about the problem.