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Visitor carles.solaz
Visitor
9,344 Views
Registered: ‎07-08-2010

Hard Macro, LUTs and power nets

Hello,

 

I'm trying to create a Hard Macro from a design for Spartan 6.

 

My design includes LUTs with different equations for the outputs O5 and O6 what means, if I didn't missunderstand, that the input A6 of the LUT must be connected to '1'.

 

So first I add a new slice "constant1" as shown in the following picture, with a constant '1' at the output A. The net name is "constant1_net".

 

2. constant1.png

 

Is this correct?

 

In second place, I remove the pins of the slice (named "qs<3>") that are connected to the power pin.

 

Then, I add a connection between the constant1 output pin and the of the slice that contains the LUTs.

 

3. inside.png

 

The equations for A6 and A5 are:

 

A6= (A6+~A6)*(~A5)

A5= 1

 

The DRC tools report the the following:

 

ERROR:PhysDesignRules:1368 - Issue with pin connections and/or configuration on block:<qs<1>_rt>:<LUT6>.  Dangling input pin. This configuration requires a signal on the input equation pins.
ERROR:PhysDesignRules:1368 - Issue with pin connections and/or configuration on block:<qs<2>_rt>:<LUT6>.  Dangling input pin. This configuration requires a signal on the input equation pins.
ERROR:PhysDesignRules:1368 - Issue with pin connections and/or configuration on block:<qs<3>_rt>:<LUT6>.  Dangling input pin. This configuration requires a signal on the input equation pins.


ERROR:PhysDesignRules:1492 - Incompatible programming for comp qs<3>. The pair of luts A5LUT and A6LUT must have a compatible equation, lower bits must be programmed the same. The A5LUT hex equation is <O5=0xFFFFFFFF> and the A6LUT hex equation is <O6=0x00FF00FF00FF00FF>.


WARNING:PhysDesignRules:1837 - Luts B5LUT and B6LUT in use in comp qs<3> with different equations without A6 pin connected to Global Logic High.
WARNING:PhysDesignRules:1837 - Luts C5LUT and C6LUT in use in comp qs<3> with different equations without A6 pin connected to Global Logic High.
WARNING:PhysDesignRules:1837 - Luts D5LUT and D6LUT in use in comp qs<3> with different equations without A6 pin connected to Global Logic High.
1 DRC errors and 6 DRC warnings.

 

 

The firt three errors and warings are due to the fact that these LUTs don't still have the constant1_net connected to A6, but what about the 4th error?

 

Morover, If I try to connect the other pins to the net the program crashes and exits.

 


Am I doing anything wrong?

 

 

Thanks.

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6 Replies
Xilinx Employee
Xilinx Employee
9,321 Views
Registered: ‎07-01-2008

Re: Hard Macro, LUTs and power nets

I don't recommend using a hard macro for slice configurations when the configuration can more easily be done with a combination of an RPM macro and directed routing constraints.  Hard macro usage should be reserved for configurations (usually IO) that map doesn't support. 

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Visitor carles.solaz
Visitor
9,311 Views
Registered: ‎07-08-2010

Re: Hard Macro, LUTs and power nets

Hi bwade.

 

I'm designing a TDC and this is why I wanted to lock the routing with the hard Macro. I could try to lock part of the design with RPM. However, am I doing anything wrong? Or is just that the tool is not meant to be used this way. I designed a TDC for Spartan 3 in the past and was quite straight forward using Hard Macros.

 

 

Carles.

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Xilinx Employee
Xilinx Employee
9,300 Views
Registered: ‎07-01-2008

Re: Hard Macro, LUTs and power nets

The net driven by a constant LUT will look like an active signal to DRC so I don't think it's going to acomplish what you want anyway. I assume you are doing this because hard macros don't support normal power/gnd nets. I think the only solution (besides using an RPM) is to avoid LUT combining so that ther is only one LUT per LUT complex.

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Visitor carles.solaz
Visitor
9,293 Views
Registered: ‎07-08-2010

Re: Hard Macro, LUTs and power nets

Hi,

 

Sounds good. Any trick to do that?

 

Thanks

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Visitor carles.solaz
Visitor
9,290 Views
Registered: ‎07-08-2010

Re: Hard Macro, LUTs and power nets

By the way, you are right, I am doing that to avoid power nets. I also tried something that worked fine for Spartan3: I tried to add a Hard Macro pin to all the A6 LUT pins so I could set to '1' this pin from the top level vhdl. This reported errors and the program eventually crashed.

Anyway, If I could avoid LUT combining It could be great. Is there any constraint or setting to avoid it?
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Xilinx Employee
Xilinx Employee
9,283 Views
Registered: ‎07-01-2008

Re: Hard Macro, LUTs and power nets

I assume that you are running some logic through a standard implementation flow and then want to convert that implementation into a hard macro. To prevent LUT combining in that initial implementation just assign a unique LUTNM property to every LUT in the design. You'll get a warning message for this use case because the tool expects to find two LUTs for each LUTNM property but I think it will work.

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