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roberthale88
Visitor
Visitor
1,728 Views
Registered: ‎08-23-2012

Help flattening design

Hi,

 

I'm trying to completely flatten my design, but am not sure if I'm going about it correctly. I select "full" for the synthesis flatten_hierarchy option. I know that Xilinx IP have some DONT_TOUCH constraints that prevent them from being completely flattened, which is fine. But it seems like my design isn't being flattened at all after Implementation. However, I don't know if I'm even looking at the right reports to be sure of this. I create the design with mostly Xilinx IP, and am not concerned about those being flattened. However, I create some of my own IP, and those I need to be at the top level. I'm attempting to fill a chip and modify the EDIF post-implementation, and porting through hierarchy is a mess, thus wanting to flatten.

 

How do I determine if the design was properly flattened? Will the Implementation hierarchy view literally have a single box, and that's it? 

 

How can I find out where flattening is being prevented if it isn't working? Does even user IP have DONT_TOUCH constraints all over?

 

Thanks for any help. 

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3 Replies
avrumw
Expert
Expert
1,724 Views
Registered: ‎01-23-2009

You say

 

However, I create some of my own IP, and those I need to be at the top level.

 

Are you using IP Integrator and trying to connect your own IP in a block diagram?

 

In this case, I am pretty sure that what you are asking can't be done (at least not by "normal" methods).

 

The flatten_hierarchy attribute affects the instances of RTL modules during synthesis. For this to have an effect, the top module and its sub-modules need to be synthesized as part of the same synthesis run.

 

This is not the default behavior of a system that uses IP integrator. In an IP integrator design, each block is an IP and is therefore synthesized "out of context" by default. The blocks are then read in as (non-flattened) sub-modules after synthesis of the top level design is complete, and hence is not affected by the flatten_hierarchy setting used for the top level module.

 

If it is possible to bring the RTL of these IP modules to the top, it is first going to be required to make then use "Global" synthesis, rather than the default "Out of Context" synthesis - perhaps someone better versed in IP integrator can tell you how to do that.

 

All this being said - why do you want to do this? Modifying edif is not something that one would normally want to do.If you really do need to make post-synthesis or post-implementation changes, you should look into the ECO capabilities of Vivado; using Tcl commands you can modify an implemented netlist... Take a look at any one of the ECO commands (like, say, "help create_cell") - it will show you all the related commands (the other ECO commands).

 

Avrum

roberthale88
Visitor
Visitor
1,682 Views
Registered: ‎08-23-2012

Avrum, 

 

Thank you!! I was wondering about whether or not even my own IP would be affected by flatten_hierarchy. I was trying to figure it out with minimal luck. I'll see if I can figure out how to get global synthesis to happen. I do have the RTL for my own IP, but yes, I've been integrating them into IP Integrator/block diagrams, since I'm using the IP repeatedly.

 

As to why I want to do this, I'm just experimenting. Really appreciate the help on the question out of left field. 

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syedz
Moderator
Moderator
1,670 Views
Registered: ‎01-16-2013

@roberthale88,

 

If your query is addressed then request you to please close this thread by marking the above port by avrum as "Accept as Solution" 

 

regarding the ECO commands you can refer to the following links: 

https://www.xilinx.com/video/hardware/vivado-engineering-change-order.html

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug904-vivado-implementation.pdf#page=150

 

--Syed

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