UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
6,699 Views
Registered: ‎10-13-2011

Help with Coregen: MMCM parameter options

Jump to solution

I am trying to create a 5 MHz clock with enable using the MMCM. I have a 60 MHz clock in my design, but I am not sure what to put for some parameters in coregen.

 

On Page 1: What should I put for "Input Jitter" and source (Single Ended Clock Capable Pin, Differential Clock Capable Pin, Global Buffer, No Buffer)?

 

On Page 2: What should I put for "Drives" (BUFGCE, BUFHCE)?

 

I understand the source might depend on the particulars of the input clock, but I really don't know where to start looking, so I would appreciate any help. I'm sure I missed some information that is required, so please explain what you need to know to help me. Thank you so much.

0 Kudos
1 Solution

Accepted Solutions
Scholar austin
Scholar
8,448 Views
Registered: ‎02-27-2008

Re: Help with Coregen: MMCM parameter options

Jump to solution

Yes,


If it is needed in more than one region, that makes it global.  Since you already have the clock in your design, and if it is already on a BUFG, the output signal name may now be connected to something else.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

0 Kudos
8 Replies
Scholar austin
Scholar
6,696 Views
Registered: ‎02-27-2008

Re: Help with Coregen: MMCM parameter options

Jump to solution

Well,

 

What do you want?


A 60 MHz clock input comes from somewhere, and has some jitter.

 

I would put in 50 ps, if you do not know, as cyrstal oscillator sources are from 25ps to perhaps as much as 100ps, depending on their quality.


As for what the output is driving:  is it to be used globally, locally?  A BUFG is the global buffer.  Look at thge MMCM user's guide for the details.

 

http://www.xilinx.com/support/documentation/user_guides/ug362.pdf

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Adventurer
Adventurer
6,692 Views
Registered: ‎10-13-2011

Re: Help with Coregen: MMCM parameter options

Jump to solution

Thanks Austin. I found this in my .PAR file. clkm is my MMCM input clk so I should set the source as global buffer, right?

 

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|                clkm |BUFGCTRL_X0Y31| No   | 4612 |  0.455     |  2.035      |

I read the document and it was pretty good information. I'm pretty sure I have available BUFG's, but the clock is only used in one component, although it is about 40% of the whole design. What is the difference between global vs local clocks though? I believe the clock will be needed in more than one region, so does that make it global?

 

Thanks

 

0 Kudos
Scholar austin
Scholar
8,449 Views
Registered: ‎02-27-2008

Re: Help with Coregen: MMCM parameter options

Jump to solution

Yes,


If it is needed in more than one region, that makes it global.  Since you already have the clock in your design, and if it is already on a BUFG, the output signal name may now be connected to something else.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

0 Kudos
Scholar austin
Scholar
6,686 Views
Registered: ‎02-27-2008

Re: Help with Coregen: MMCM parameter options

Jump to solution

It is fanned out (connected) to over 4,000 other elments (loads).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Adventurer
Adventurer
6,668 Views
Registered: ‎10-13-2011

Re: Help with Coregen: MMCM parameter options

Jump to solution

I have gotten an error when trying to synthesize in PlanAhead. If my clock buffer is going to be used in a reconfigurable partition, then I must choose BUFHCE, not BUFGCE?

0 Kudos
Scholar austin
Scholar
6,666 Views
Registered: ‎02-27-2008

Re: Help with Coregen: MMCM parameter options

Jump to solution

Yes.

 

Reconfigurability adds a number of restrictions.



Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Adventurer
Adventurer
6,664 Views
Registered: ‎10-13-2011

Re: Help with Coregen: MMCM parameter options

Jump to solution

Any other restrictions that I need to be aware of ahead of time? I wish to have a dynamic partition covering multiple clock domains. Am I better off putting the buffer as a BUFGCE in the static logic or having a BUFHCE in the reconfigurable logic?

0 Kudos
Scholar austin
Scholar
6,662 Views
Registered: ‎02-27-2008

Re: Help with Coregen: MMCM parameter options

Jump to solution

I recommend putting the basic structure stuff in the non-reconfigurable part.

 

IO, clocks, etc. are best all kept static.

 

Change the logic all you wish.

 

That is the simplest and easiest to do, and will lead tio the fewest headaches and problems.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos