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Visitor kobe0294
Visitor
1,018 Views
Registered: ‎01-30-2018

How Constraining Routing not route through a certain CLB?

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Hi, I am trying to find a method to constrain PAR to not route through or switch box of a CLB. You can block PAR from placing any Logic onto a CLB by using the constraints CONFIG PROHIBIT..Basically it leaves the slices in the CLB "empty"...But PAR uses the switch matrix of such an "empty" CLB to route through to other slices. Is there any other way to block PAR from using switch matrix of such "empty" CLBs for routing. Thanks in advance!! 

 

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Moderator
Moderator
1,439 Views
Registered: ‎01-16-2013

Re: How Constraining Routing not route through a certain CLB?

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@kobe0294,

 

draw a pblock for dummy logic and set contain_routing property on the pblock. Check page 173 in below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug912-vivado-properties.pdf#page=173

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Visitor kobe0294
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992 Views
Registered: ‎01-30-2018

Re: How Constraining Routing not route through a certain CLB?

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More info for your reference:

we have a V7-2000T FPGA IC, and found that the power supply for BANK39 was short,
We want re-use this FPGA , so need to place and route bypass the damaged area.

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Moderator
Moderator
1,440 Views
Registered: ‎01-16-2013

Re: How Constraining Routing not route through a certain CLB?

Jump to solution

@kobe0294,

 

draw a pblock for dummy logic and set contain_routing property on the pblock. Check page 173 in below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug912-vivado-properties.pdf#page=173

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------