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greatmaverick
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Registered: ‎04-06-2017

How FPGA implementation satisfies the output delay constraint?

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If I set output delay constrant to satisfy the hold time, how the implementation tool satisfies the output delay? What happens to the implemented design that contributes to the desired result?

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389 Views
Registered: ‎01-22-2015

@greatmaverick 

I think the vivado adjust the position of the DFF and routing to meet the constraint. Is this understanding correct?

If the launch flip-flop (DFF) is located in the FPGA fabric then Vivado implementation will move the DFF or reroute signals from the DFF to the IO pin - attempting to help the interface pass timing analysis.  So, your understanding is correct. 

However, these actions by Vivado are usually not enough to make the interface pass timing analysis.  So, often we must manually add other components (eg. IDELAY block) to the circuit to make the interface pass timing analysis.

Also, for interface circuits, we usually don't want Vivado implementation attempting to make the circuit pass timing analysis.  -because, this means that the timing of the interface can change from implementation to implementation.  So, we usually locate the FPGA circuits (DFF, IDELAY, ODDR, etc) for the interface in the IOB of the FPGA.  When circuits are located in the IOB, they have fixed position and fixed routing, which cannot be changed/adjusted by Vivado implementation.

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9 Replies
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Registered: ‎01-22-2015

I assume you are talking about a Source-Synchronous Interface (SSI) between the FPGA and an external device (eg. a digital register).

The set_output_delay constraints for an SSI describe the external circuits (board trace delays and setup/hold of the external device).  The set_output_delay constraints do not (as you say) "set output delay constrant to satisfy the hold time".

Components (register, ODDR, ODELAY) inside the FPGA that connect to the SSI are usually locked into position in the IOB.  That is, when implementation sees that the SSI is not passing timing analysis, it usually cannot "move things around" to help the SSI pass timing analysis. 

Thus, it is up to you to place an ODELAY on either the clock or data line of the SSI - and adjust the ODELAY until the SSI passes timing analysis.

Cheers,
Mark

greatmaverick
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Registered: ‎04-06-2017

I use vivado and kintex-7 FPGA. as I increase the output delay constraint to the negative direction, the data valid time after the output clock increases. I do not modify other source file. I do.not explicitly call the odelay. I think vivado do It automatically. I hope my description can be confirmed.

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Registered: ‎01-22-2015

…as I increase the output delay constraint to the negative direction…

The set_output_delay constraints are NOT an adjustment and they do NOT create a delay.  Instead, these constraints provide information to timing analysis.  I will demonstrate this with the following example circuit for a Source Synchronous (output) Interface (SSI). 

FPGA_src_sync_output.jpg

Note how the FPGA is sending both a clock and data to the external device (a register).  The quantities, t_pxc and t_pxd are propagation delays for the board traces associated with the clock and data of the SSI.  The quantities, t_sux and t_hdx, are setup and hold requirements for the external device.

For the above SSI, the delay used in the “set_output_delay -max” constraint is calculated as  (t_pxd - t_pxc + t_sux).  The delay used in the “set_output_delay -min” constraint is calculated as  (t_pxd - t_pxc - t_hdx).  As you can see, the set_output_delay constraints provide information to timing analysis about circuits outside the FPGA.

 

I do.not explicitly call the odelay. I think vivado do It automatically.

If the SSI does not pass timing analysis YOU must add ODELAY components – to either the clock or data output of the FPGA.  Also, you must manually adjust ODELAY until the SSI passes timing analysis.  Vivado will NOT automatically add ODELAY.  Vivado will NOT automatically adjust ODELAY.

avrumw
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Registered: ‎01-23-2009

Just a quick addendum. There are some other ways of fixing these hold times - you can use a different internal clock for the forwarded clock and the forwarded data. For some SDR interfaces, you may be able to meet timing by inverting the outgoing clock. This is done by swapping the D1 and D2 of the ODDR forwarding the clock (D1=0, D2=1) and modifying the create_generated_clock on the ODDR to include the -invert flag. 

You can also use different clocks from the same MMCM (using two identical clock buffers) for the clock and the data - i.e.use CLKOUT0 (via a BUFG) for the forwarded data and CLKOUT1 (via another BUFG) for the forwarded clock. Now you can use the PHASE_SHIFT capabilities of the MMCM to introduce a phase shift between these two clocks. If this is UltraScale/UltraScale+/Versal then you need to put the two clock nets (the outputs of the BUFGs) in the same CLOCK_DELAY_GROUP to instruct the tool to balance the clock insertion delay of these two clocks.

Avrum

greatmaverick
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Registered: ‎04-06-2017

As I increase the output delay constraint to the negative direction, the data valid time after the output clock increases.I find the result through post layout timing simulation. How can I explain the result which I think is a contradiction from your description?

Thank you

 

drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

interesting 

   can you make a demo project you can share ? 

    

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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greatmaverick
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Registered: ‎04-06-2017

Thank you. I have compared the layout and routing with and without output delay constraint. I've found in the two different cases, the D flip-flop that outputs data are in different slices, resulting different time required for a signal to travel to the IO pin. I think the vivado adjust the position of the DFF and routing to meet the constraint. Is this understanding correct?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

Can you share the demo project please.

 

The tools as I understand it , 

   run till complete  or fails.

What you are seeing is entirely within the above description.

   The tools start up with a guess as to placement / system,

        Traditionaly, the tools would not move IO registers to meet outptu timming, just report if they had passed , and by how much,

              but its entirely possible that they have changed over versions, and I'm behind the 10 ball,

                  and can try to place register to meet your timing, that does not mean the tool is adding IO delay , 

 

Show us the demo's.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Registered: ‎01-22-2015

@greatmaverick 

I think the vivado adjust the position of the DFF and routing to meet the constraint. Is this understanding correct?

If the launch flip-flop (DFF) is located in the FPGA fabric then Vivado implementation will move the DFF or reroute signals from the DFF to the IO pin - attempting to help the interface pass timing analysis.  So, your understanding is correct. 

However, these actions by Vivado are usually not enough to make the interface pass timing analysis.  So, often we must manually add other components (eg. IDELAY block) to the circuit to make the interface pass timing analysis.

Also, for interface circuits, we usually don't want Vivado implementation attempting to make the circuit pass timing analysis.  -because, this means that the timing of the interface can change from implementation to implementation.  So, we usually locate the FPGA circuits (DFF, IDELAY, ODDR, etc) for the interface in the IOB of the FPGA.  When circuits are located in the IOB, they have fixed position and fixed routing, which cannot be changed/adjusted by Vivado implementation.

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