03-29-2014 06:16 AM
There is an example design in Xilinx, which connects 60 GPIO pins of Zync Processing System to different pins of FPGA. I want the LED pins to be driven by a different, custom core. I can replace the LED connections from Zync PS to my core. But, Zync will still drive corresponding pins and the map will connect them to arbitrary ports of FPGA, I believe. Can I tell the mapper that this is unncecessary?
03-31-2014 01:48 AM
here are the 3 possibities:
if you don't constrain all I/O ports of your toplevel design, the Xilinx tools will choose and pick a location for you.
This is potentially dangerous and not recommended.
However, you can have I/O ports and constrain them in UCF which you don't use. The Xilinx tools will then tristate these unused ports.
It will not be allowed to have I/O constraints in the UCF which do not exist in your toplevel. The tools should normally error out on these.
04-01-2014 02:14 AM
You should consider using Vivado for new designs. It is our recommended tool for Zynq designs.