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Visitor dh0414.lee
Visitor
489 Views
Registered: ‎01-24-2018

How can I make success implementation using DDR4 source without DDR4 xci IP

Hi.

 

How can I make success implementation using DDR4 source without DDR4 xci IP?

 

here is my sequence.

1. I make a project and create MIG DDR4 IP (default ddr4_0.xci)

2. I make example design and change xdc pin mapping.

   - The pin mapping is board dependent so can not change.

3. Run synthesis and open synthsis design

4. I export constraints file and change xdc file

5. I remove xci file and add MIG source files

 (default example design path) to ddr4_0_ex -> ddr4_0_ex.srcs -> sources_1 -> ip -> ddr4_0 ->

       Add files

             1. rtl -> ip_top -> (ddr4_0_ddr4_mem_intfc.sv, ddr4_0_ddr4.sv, ddr4_0.sv)

             2. ip_0 -> ddr4_0_microblaze_mcs.xci 

       Add directories

            1. rtl -> axi

            2. rtl -> axi_ctrl

            3. rtl -> cal

            4. rtl -> clocking

            5. rtl -> controller

            6. rtl -> ui

            7. ip_1 -> rtl

 

Then, synthesis is successful but Implementation generate error!!

-  the error message is BITSLICE error because constraint conflict

 

How can I get constraints file for synthesis and Implementation with MIG source files?

 

 

 

 

 

 

 

 

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1 Reply
Moderator
Moderator
487 Views
Registered: ‎09-15-2016

Re: How can I make success implementation using DDR4 source without DDR4 xci IP

Hi @dh0414.lee

 

It is highly recommended to add IP .xci file to the project rather than the RTL source files or dcp. Please have a better look at this AR:

https://www.xilinx.com/support/answers/69690.html

 

Regards

Rohit

 

Regards
Rohit
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