How to LOC multiple CFGLUT5 instances in the same Slice

[Lohil]

Hello,

I've been trying to place multiple CFGLUT5s on the same slice but I keep running into this 'Cannot set LOC property' issue.

For example given two sets of constraints:

set_property BEL A6LUT [get_cells A1/CFGLUT5_inst]
set_property LOC SLICE_X38Y49 [get_cells A1/CFGLUT5_inst]

set_property BEL B6LUT [get_cells A2/CFGLUT5_inst]
set_property LOC SLICE_X38Y49 [get_cells A2/CFGLUT5_inst]

I get the critical warning:
[Vivado 12-2285] Cannot set LOC property of instance 'A2/CFGLUT5_inst/S1'... Instance A2/CFGLUT5_inst/S1 can not be placed in A6LUT of site SLICE_X38Y49 because the bel is occupied by A1/CFGLUT5_inst/S1. This could be caused by bel constraint conflict . . .

But I don't understand how this error could be coming up, I think I'm explicitly saying place A2/CFGLUT5_inst at B6LUT not at A6LUT as vivado is saying. (A1 is indeed correctly placed at X38Y49 A6LUT)

The error persists even if I detail where to place S1 and S2 (an SRL16E & SRL32E respectively) or if I don't make any BEL statement at all and just let the tool try to figure out how to fit them both.

I'm implementing the CFGLUT5 off the basic lang. template:

-- CFGLUT5: Reconfigurable 5-input LUT (Mapped to SliceM LUT6)
-- Artix-7
-- Xilinx HDL Language Template, version 2019.2

CFGLUT5_inst : CFGLUT5
generic map (
INIT => X"FF0FF0FF")
port map (
CDO => CDOa(0), -- Reconfiguration cascade output
O5 => Oa5(0), -- 4-LUT output
O6 => Oa6(0), -- 5-LUT output
CDI => CDIa(0), -- Reconfiguration data input
CE => CEa(0), -- Reconfiguration enable input
CLK => CLK, -- Clock input
I0 => Ia0(0), -- Logic data input
I1 => Ia1(0), -- Logic data input
I2 => Ia2(0), -- Logic data input
I3 => Ia3(0), -- Logic data input
I4 => Ia4(0) -- Logic data input
);

Any insight appreciated
Thank you

[hongh]

Hi, @Lohil ,

Could you provide your opt.dcp?

[Lohil]

Well I can't share the actual project, but I've created a toy example which should hopefully approximate the issue, it does indeed trigger the same error.

In the opt.dcp  it would also appear vivado is trying to place the two on top of one another.

[hongh · Accepted solution]

The LUT with cascade in will always be placed in ALUT of SLICE. That's the reason for the conflicting.

If you use the other normal LUT, the conflict will not happen.

[Lohil]

Ah okay I see now, only ALUT has its M32 pin capable of going out of the slice while the others just cascade to the adjacent LUT... missed that, oh well back to the drawing board