We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
I met a very general question in ISE Place & Route phase.
The problem is how to prevent place & route program being trapped by corner area?
This is very common issue when I met a timing failure.
To be detailed, please see picture below. Here's snapshot I captured as example.
The four red circle area are places of high risk! Most of timing failure is proved to occur around these area.
Based on my understanding, I tried to add as few constraint as possible. I only constraint those very high speed interface and high speed arithmetic circuit (with pblock). However, the design often gets trapped by these area. The failure path is often trivial path, which is considered to be not timing critical. The reason of failure is P&R program tries to route around these four area, which leads to long trace than expected. So, my question is if there's way to guide ISE avoid to place thing around these area? Or should I use pblock to lock most of thing to elude?