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Registered: ‎03-28-2015

How to avoid Place & Route being trapped?

Hello guys, 

I met a very general question in ISE Place & Route phase. 

The problem is how to prevent place & route program being trapped by corner area?

This is very common issue when I met a timing failure.


To be detailed, please see picture below. Here's snapshot I captured as example. 

The four red circle area are places of high risk! Most of timing failure is proved to occur around these area.

Based on my understanding, I tried to add as few constraint as possible. I only constraint those very high speed interface and high speed arithmetic circuit (with pblock). However, the design often gets trapped by these area. The failure path is often trivial path, which is considered to be not timing critical. The reason of failure is P&R program tries to route around these four area, which leads to long trace than expected. So, my question is if there's way to guide ISE avoid to place thing around these area?  Or should I use pblock to lock most of thing to elude? 


Appreciate for your time, and thanks advance! 





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Xilinx Employee
Xilinx Employee
Registered: ‎05-08-2012

Re: How to avoid Place & Route being trapped?

Hi @poorren. Having a second pblock could help in this case to keep the logic from spreading to regions that are difficult to route around. An alternative to using a pblock is to set PROHIBIT constraints on sites that can cause a problem. I also see that the "“UAP_DENSMAP_CFG_NEIGHBORHOOD_SLOPE=1" environmental parameter is suggested on page 4 of White Paper 381. 




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