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Explorer
Explorer
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Registered: ‎08-15-2014

How to avoid SLR crossing to improve timing

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hi,

There is a large delay in P&R result. it is mainly caused by route delay (>90%).

And I  found there is SLR crossing. how to avoid SLR crossing to reduce route delay?

 

SLR_CROSS.png
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Moderator
Moderator
242 Views
Registered: ‎11-04-2010

Re: How to avoid SLR crossing to improve timing

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Hi, @jeffson ,

You can create pblocks ranged one SLR and assign the proper logic to the different SLR pblocks.

For the cross-SLR path, promise it's FF-> FF structure and fanout equals 1.

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: How to avoid SLR crossing to improve timing

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Hi, @jeffson ,

You can create pblocks ranged one SLR and assign the proper logic to the different SLR pblocks.

For the cross-SLR path, promise it's FF-> FF structure and fanout equals 1.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: How to avoid SLR crossing to improve timing

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Hi @jeffson ,

Also you can try the properties USER_SLR_ASSIGNMENT,  USER_CROSSING_SLR, and USER_SLL_REG also.

For detailed information, please check below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug912-vivado-properties.pdf

Thanks,

Raj

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Explorer
Explorer
224 Views
Registered: ‎08-15-2014

Re: How to avoid SLR crossing to improve timing

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Thanks hongh,

As I don't care where registers are placed? is it possible to solve this problem just via put some pipes into this path. 

for example:

formerly: FF0(in SLR2)  <-----> OSERDES(in SLR3) 

Now: FF0(in SLR2) <----->  FF1(in SLR3)   <-----> OSERDES(in SLR3)

If I add some pipes into this path as beyond, will vivado implement a reduced route delay?

 

 

 

 

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Moderator
Moderator
214 Views
Registered: ‎11-04-2010

Re: How to avoid SLR crossing to improve timing

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Hi, @jeffson ,

With the method you mentioned, you can try to set the below property for 2 FFs:

USER_SLR_ASSGINMENT

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