04-16-2020 01:15 AM
hi,
There is a large delay in P&R result. it is mainly caused by route delay (>90%).
And I found there is SLR crossing. how to avoid SLR crossing to reduce route delay?
04-16-2020 01:21 AM
Hi, @jeffson ,
You can create pblocks ranged one SLR and assign the proper logic to the different SLR pblocks.
For the cross-SLR path, promise it's FF-> FF structure and fanout equals 1.
04-16-2020 01:21 AM
Hi, @jeffson ,
You can create pblocks ranged one SLR and assign the proper logic to the different SLR pblocks.
For the cross-SLR path, promise it's FF-> FF structure and fanout equals 1.
04-16-2020 01:25 AM - edited 04-16-2020 01:25 AM
Hi @jeffson ,
Also you can try the properties USER_SLR_ASSIGNMENT, USER_CROSSING_SLR, and USER_SLL_REG also.
For detailed information, please check below link:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug912-vivado-properties.pdf
Thanks,
Raj
04-16-2020 01:39 AM
Thanks hongh,
As I don't care where registers are placed? is it possible to solve this problem just via put some pipes into this path.
for example:
formerly: FF0(in SLR2) <-----> OSERDES(in SLR3)
Now: FF0(in SLR2) <-----> FF1(in SLR3) <-----> OSERDES(in SLR3)
If I add some pipes into this path as beyond, will vivado implement a reduced route delay?
04-16-2020 01:53 AM
Hi, @jeffson ,
With the method you mentioned, you can try to set the below property for 2 FFs:
USER_SLR_ASSGINMENT