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Adventurer
Adventurer
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Registered: ‎07-21-2020

How to constrain differential input clock

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I am using the Arty S7 50 board. I have an external differental clock signal which I want to feed into the Arty. 

I don't know how to constrain the differential input clock in my XDC file. Constraining them like this doesn't seem to work:

set_property CLOCK_DEDICATED_ROUTE FALSE { LOC N15 IOSTANDARD LVDS25 } [get_nets { CLK_P}]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
set_property CLOCK_DEDICATED_ROUTE FALSE { LOC P16 IOSTANDARD LVDS25 } [get_nets { CLK_N}]; #IO_L12N_T1_MRCC_14 Sch=jb_n[4]

Does somebody know how the correct syntax looks like?

 

 

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Registered: ‎06-21-2017

No.  These must be turned into a single ended clock to use inside the FPGA.  You can use both the rising edge and falling edge of the single ended clock or you can use the clocking wizard to create two single ended clocks 180 degrees out of phase.  In most cases, it's a better idea to stick with just the rising edge.  Why do you want to use both edges? 

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887 Views
Registered: ‎06-21-2017

What error are you getting?

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Adventurer
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Registered: ‎07-21-2020

@bruce_karaffa 

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: CLK_N.


[DRC UCIO-1] Unconstrained Logical Port: 1 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: CLK_N.

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Adventurer
Adventurer
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Registered: ‎07-21-2020

@bruce_karaffa 

I am getting this errors for the negative clock:

 

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: CLK_N.

 

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: CLK_N.

 

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Registered: ‎06-21-2017

If the differential clock is going into a differential input buffer, you should not need to define the pin LOC for the _n side of the signal.  If the differential signal is not going into a differential buffer or if the _p and _n halves of the signal are not going into a differential pin pair, you won't get LVDS.  What does your code look like where the signal is brought into the FPGA?

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Adventurer
Adventurer
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Registered: ‎07-21-2020

@bruce_karaffa 

They go into a differential pin pair. I actually don't instantiated a differential input buffer.
My top level domain looks like this for the input clock:

Port(
CLK_P: in std_logic;
CLK_N: in std_logic
....
);

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Registered: ‎06-21-2017

Does the pair go into a clocking wizard?  If not, how does the signal get used in the FPGA?

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Adventurer
Adventurer
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Registered: ‎07-21-2020
@bruce_karaffa the signal doesn't go into the clocking wizard. The signal is used as the "main" clock. Processes are based on both clocks.

Example:
process(CLK_N, CLK_P)
begin
if(rising_edge(CLK_P) then
...
end if;
if(rising_edge(CLK_N) then
...
end if;
end process;
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Registered: ‎06-21-2017

That's your problem.  If you want to use the signal as a differential pair, you need to use a differential buffer to translate the differential signal to a single ended signal at the internal voltage of the FPGA.  You cannot use the _p or _n signals as single ended clocks in the FPGA.  The clock wizard is the best way to go here  Check the differential input box.  It will create the input buffer, an MMCM to condition the clock and derive other phases and frequencies if you want and create clock buffers for all related clocks.

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Adventurer
Adventurer
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Registered: ‎07-21-2020

Ok thank you that makes sense. But can I still use both clocks (CLK_N and CLK_P) to clock processes?

 

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Registered: ‎06-21-2017

No.  These must be turned into a single ended clock to use inside the FPGA.  You can use both the rising edge and falling edge of the single ended clock or you can use the clocking wizard to create two single ended clocks 180 degrees out of phase.  In most cases, it's a better idea to stick with just the rising edge.  Why do you want to use both edges? 

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Adventurer
Adventurer
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Registered: ‎07-21-2020

Thanks again. I need to use both edges at least. I am getting data from a device on both rising edges of CLKN and CLKP. But using rising and falling edge of CLKP equals using rising edge of CLKN and CLKP.

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781 Views
Registered: ‎06-21-2017

In that case, you should use an Input Double Data Rate register (IDDR)  Look in the language templates for it.

Adventurer
Adventurer
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Registered: ‎07-21-2020

Can you tell me where exactly I can find this template?

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Registered: ‎06-21-2017

vivado=>tools=>language templates=>VHDL=>Device Primitive Instantiation=> (FPGA family) =>I/O Components=>DDR Registers=>Input DDR Register (IDDR)

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Adventurer
Adventurer
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Registered: ‎07-21-2020

@bruce_karaffa I am getting data on the rising edge of CLKP and rising edge of CLKN (differential clock). 

As you said I am using the clocking wizard to turn this differential clock into a single ended clock(CLKS). 

Using the rising and falling edge of the CLKS is the same as using the rising edge of CLKP and CLKN, right? 

Then I wouldn't need a IDDR. Or did I miss something here?

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Registered: ‎06-21-2017

You can do what you are proposing.  Vivado won't be able to use an input register, rather it will just use a buffer and branch your signal to to internal registers.  The IDDR will give you more consistent timing, since the register is right at the input of the FPGA, thus will not change with placement.  You will be using only one clock, so the tool does not need to deal with skew between two clocks.  All in all, the IDDR will provide more consistent timing and will be able ro run at a higher frequency.

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