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1,332 Views
Registered: ‎11-05-2017

How to constrain layout of module?

I have a module that contains some combinatorial logic that can be mapped to fit in one slice. I was wondering if there was a way to force this module to be fit in one slice without having to specify the placement of each LUT.

 

Vivado does sometimes optimize the module into one slice, is there a way I can save this configuration from the floorplanning window as a macro of some sorts, so the module will always maintain the same relative layout within each slice?

 

This module is used thousands of times, so manually placing them is not an option.

 

 EDIT: Basically I'm trying to avoid having to manually map the combinatorial logic to LUTs, I'd rather let Vivado do it once and save the results for future use.

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Scholar
Scholar
1,323 Views
Registered: ‎02-27-2008

Re: How to constrain layout of module?

https://www.youtube.com/watch?v=hJ1LaSKYYow

 

Is this useful?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Mentor
Mentor
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Registered: ‎02-24-2014

Re: How to constrain layout of module?

I would suggest that you bite the bullet and just use code that places the logic where you want it.  Using XDC constraints is tricky, and not very amenable to being parameterized in your source code.    Since you are making a module that will be repeated many times, crafting a good solution will pay dividends in the future.    You will want to use RLOC constraints, so that LUT addressing location is relative to the lower left corner of your module.   RPM design in RTL can be a very powerful technique.

Don't forget to close a thread when possible by accepting a post as a solution.
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Highlighted
1,230 Views
Registered: ‎11-05-2017

Re: How to constrain layout of module?

I've been trying to use RLOCs and they work to some extent, but I can't seem to prevent opt_design from removing elements. It seems that once opt_design removes a single RLOC element it messes up the whole thing. If I don't run opt_design the RLOCs work correctly.

 

Searching for information on RLOCs, KEEP attributes, DONT_TOUCH, etc... half the information is outdated and doesn't apply anymore. I was using LUT_MAP for a while but apparently that doesn't do anything anymore, so now I am using truth table strings with the LUT macros. I don't understand why Xilinx makes manual floorplanning so difficult.

 

 

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Xilinx Employee
Xilinx Employee
1,222 Views
Registered: ‎09-20-2012

Re: How to constrain layout of module?

Hi @christian1188

 

Are you using XDC macros? 

 

Refer to "XDC macros" section in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug903-vivado-using-constraints.pdf 

 

Look at the examples given in "managing macros" section.

Thanks,
Deepika.
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