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noreeli79
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Registered: ‎11-04-2015

How to constraint a flancter

Good afternoon,

 

I am trying to use a flancter module in my Kintex design (Vivado 2015.4). That flancter module captures a pulse from one clock domain two a second clock domain.

The pulse to be caught is connected to a clock input of a flip flop (set_clk flop).

 

When using that flancter module several times (> 500), I get a "No clocks" warning on Timing Summary. The clock of that set_clk flop

is listed for each flancter instance.

 

So I try to constraint it in the following manner (in a tcl file):

 

set cnt 0
foreach i [get_pins -hierarchical *Flancter.setflop_reg/C] {
    set cnt [expr $cnt + 1]
    create_clock -period 8.000 -name myFla$cnt -add $i  
}

 

But that constraint seems to overcharge Vivado, it stops with a "Out of memory" error message (I have 32G of memory).

How can I constraint my flancter modules more smoothly?

 

Thank you, noreeli

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avrumw
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Registered: ‎01-23-2009

You can't.

 

This type of circuit is inherently asynchronous - you are using a clock pin of a flip-flop as an asynchronous signal. The "clock" is not periodic, and hence trying to constrain it as a periodic signal is meaningless.

 

I have no idea why you would want to use this circuit (at all) - forget about using 500 instances of it.

 

What are you trying to do? Unless this is a reasearch topic on this particular circuit, this is not a circuit you should consider implementing in an FPGA.

 

Avrum

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noreeli79
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Registered: ‎11-04-2015

We are using that kind of flancter in different FPGA projects extensively and successfully (non-Xilinx). It is in our designer's toolbox.

As I stated before we use it to pass single clock events from one clock domain to a second.

 

By the way: The design is from Doulos, see http://www.doulos.com/knowhow/fpga/fastcounter/

 

Noreeli

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avrumw
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Registered: ‎01-23-2009

I am not a fan of this circuit. It (and some closely related relatives, where a data pulse is brought into a clock, asynchronous preset or asynchronous clear port) do as you say, but I would only consider using them when I don't have access to the source clock domain. If you do have access to the source clock domain, I prefer the toggle event synchronizer:

 

Untitled.gif

 

 

This synchronizer has a number of advantages:

  - it is "more" synchronous; no synchronizer is completely synchronous, but this circuit does not have data signals connected to clock or asynchronous pins

  - it is faster - you can have one pulse the longer of every src_clk period or every >1 (more safely 2) dst_clk periods

  - it does not need any special constraint for the event_toggle register (i.e. no "create_clock")

  - it is recognized by most clock domain crossing (CDC) analysis tools

  - when you consider the extra synchronizer required by the flancter, it is probably smaller

 

But again, you MUST have access to the src_clk domain to do this - but this will be the case in most circumstances...

 

And, of course, like all synchronizers, this does need some constraints - the ASYNC_REG proprety needs to be set on both of the metastability resolution flip-flops (in the dotted box) and an exception needed between the event_toggle_reg and signal_meta_reg (preferably a set_max_delay -datapath_only).

 

But, one wonders why you need 500+ of these?

 

As I have said in other posts, there is no "one size fits all" solution for clock crossing. These clock crossers (the toggle event and the flancter) are specifically for fast pulse events going between domains. For slow pulse events, they are overkill - there are simpler circuits available. For any other type of clock crossing (slow changing status signals, or busses of any kind), these are not appropriate CDC circuits.

 

So, while it is not impossible to have a system with 500+ independent pulse events crossing domains, its pretty uncommon. I would worry that this circuit was being used as a "catch all" synchronizer, and hence used in places where it isn't appropriate. Even if there are truly 500+ independent pulse events, one wonders if there is a different clocking architecture that would allow you to do more processing in the source domain in order to reduce the number of clock crossing paths (its always a good idea to reduce the number of clock crossing paths - even properly handled, these are a source of potential system failure).

 

Avrum

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noreeli79
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Registered: ‎11-04-2015

>But, one wonders why you need 500+ of these?

 

 

I have for example 64 rx interfaces (each of these running with its own clock) which are indicating several events (i.e. checksum errors, header errors etc.) to a central processor interface (which is running with a different clock).

 

Noreeli

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