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leonardooalves
Observer
Observer
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Registered: ‎11-24-2020

How to constraint the AXI Ethernet IP

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Hi, I hope you are well.

I have a BD with an AXI Ethernet IP for the Zynq ZCU102. It synthesizes the IP but generates errors during the implementation, which seems to be due to missing constraints. However, I could not find how to constraint that.

Errors:

 

Opt Design: [Designutils 20-4126] Site Type for the Routed site (BITSLICE_RX_TX) and element pin (BITSLICE_RXTX_RX) do not match for site BITSLICE_RX_TX_X0Y6
Place Design:

[Place 30-687] Expected cell design_1_i/gfe_subsystem/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_5[1].Gen_5_1.Gen_5_1_1.Nibble_I_RxBitslice_0 be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.

[Place 30-687] Expected cell design_1_i/gfe_subsystem/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_7[5].Gen_7_1.Nibble_I_TxBitslice be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.

[Place 30-99] Placer failed with error: 'Placer initialization failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

 

I have tried to place it automatically, but it failed.

 

place_ports sgmii_phyclk_clk_n sgmii_phyclk_clk_p sgmii_lvds_rxn sgmii_lvds_rxp sgmii_lvds_txn sgmii_lvds_txp mdio_io mdio_mdc {phy_reset_out[0]}
ERROR: [Place 30-686] Cell design_1_i/gfe_subsystem/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_5[1].Gen_5_1.Gen_5_1_1.Nibble_I_RxBitslice_0 is used in native BITSLICE mode. It is required that the connected I/O port sgmii_lvds_rxn to have location constraint. All IO Interfaces using Native Mode must have valid Package Pin assignments. Native Mode IO Interfaces typically come from UltraScale MIG IP or the UltraScale High-Speed Select IO Wizard. Please correct design constraints.
ERROR: [Place 30-686] Cell design_1_i/gfe_subsystem/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_5[2].Gen_5_1.Gen_5_1_0.Nibble_I_RxBitslice_n is used in native BITSLICE mode. It is required that the connected I/O port sgmii_lvds_rxn to have location constraint. All IO Interfaces using Native Mode must have valid Package Pin assignments. Native Mode IO Interfaces typically come from UltraScale MIG IP or the UltraScale High-Speed Select IO Wizard. Please correct design constraints.
ERROR: [Place 30-686] Cell design_1_i/gfe_subsystem/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_7[5].Gen_7_1.Nibble_I_TxBitslice is used in native BITSLICE mode. It is required that the connected I/O port sgmii_lvds_txn to have location constraint. All IO Interfaces using Native Mode must have valid Package Pin assignments. Native Mode IO Interfaces typically come from UltraScale MIG IP or the UltraScale High-Speed Select IO Wizard. Please correct design constraints.
ERROR: [Vivado 12-637] Placer DRC check failed, Please see the previously displayed individual error or warning messages for more details.

 

 

Can someone help with how to constraint that? (I added the PDF of the system and a screenshot of the IP settings).

Thank you in advance.

AXI_ETHERNET_IP.png
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1 Solution

Accepted Solutions
syedz
Moderator
Moderator
540 Views
Registered: ‎01-16-2013

@leonardooalves 

 

From the error message, the location constraints should come from the IP when generated. Open the synthesized design and in IO planning layout you can verify the ports mentioned have location constraints.

It is required that the connected I/O port sgmii_lvds_rxn to have location constraint. All IO Interfaces using Native Mode must have valid Package Pin assignments. Native Mode IO Interfaces typically come from UltraScale MIG IP or the UltraScale High-Speed Select IO Wizard. Please correct design constraints.

 

You can also right-click on the ethernet IP (.xci file or bd cell) and select open example design. This will open IP example design and you can run the implementation to see if you see placement error. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

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2 Replies
syedz
Moderator
Moderator
541 Views
Registered: ‎01-16-2013

@leonardooalves 

 

From the error message, the location constraints should come from the IP when generated. Open the synthesized design and in IO planning layout you can verify the ports mentioned have location constraints.

It is required that the connected I/O port sgmii_lvds_rxn to have location constraint. All IO Interfaces using Native Mode must have valid Package Pin assignments. Native Mode IO Interfaces typically come from UltraScale MIG IP or the UltraScale High-Speed Select IO Wizard. Please correct design constraints.

 

You can also right-click on the ethernet IP (.xci file or bd cell) and select open example design. This will open IP example design and you can run the implementation to see if you see placement error. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

leonardooalves
Observer
Observer
501 Views
Registered: ‎11-24-2020

Thank you very much. It worked! I opened an example design, run the implementation, and checked how the pins were set. Then, for the project where the constraints weren't generated automatically, I inserted in the constraint file the following:

 

# ----- Ethernet IP -----
#lvds_clk
set_property PACKAGE_PIN AE7 [get_ports sgmii_phyclk_clk_p]
set_property IOSTANDARD LVDS [get_ports {sgmii_phyclk_clk_p}]
#mdio - mdc
set_property PACKAGE_PIN AG3 [get_ports mdio_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports {mdio_mdc}]
#mdio - mdio
set_property PACKAGE_PIN AD4 [get_ports mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports {mdio_io}]
#RST.phy_rst_n
set_property PACKAGE_PIN AJ2 [get_ports phy_reset_out]
set_property IOSTANDARD LVCMOS18 [get_ports {phy_reset_out}]
#sgmii_lvds
set_property PACKAGE_PIN AH4 [get_ports sgmii_lvds_txp] 
set_property IOSTANDARD LVDS [get_ports {sgmii_lvds_txp}]
set_property PACKAGE_PIN AJ6 [get_ports sgmii_lvds_rxp] 
set_property IOSTANDARD LVDS [get_ports {sgmii_lvds_rxp}]

 

 That allowed my project to set the Axi Ethernet pins like in the example, and get rid of the errors.

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