07-23-2009 01:33 AM
I'm currently working on some VHDL projects and it seems interesting for us to generate reusable netlist.
Unfortunately I didn't found the information to generate these files from Xilinx ISE 10.1.
I need to create *.ngc and *.xco files and then to re-import them into other projects.
Does someone know the way to generate such files?
Thanks in advance and best regards,
07-25-2009 10:21 AM
If you want to create a netlist of a module then you need to create a new ISE project with that particular module as top module and XST to create the netlist (.ngc) file, when you are doing so make sure that the XST option "ADD I/O BUFFERS" is disabled. You can as well run XST in command line, if you don't want to create a separate project.
But you won't be able to generate the xco file, however, if you create a hdl wrapper to the netlist and the wrapper to your main project. The tools should be able to read the netlist.
you should also make sure that the XST option "core search directory" and Translate option "Macro search path" are set, for the tool to read the netlists form that directory.
06-18-2010 11:26 AM
Can I instantiate some componentes created by CoreGen in my module and create a .ngc from it to be reused in other project?
03-06-2011 02:33 PM